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2.0 Pin Descriptions (Continued)

RXCLK/

RXPMACLK1

156

Receive Clock: A continuous clock, sourced by an external PMD device, that is

recovered from the incoming data. During 1000 Mb/s mode RX_CLK is 125

MHz, during 100 Mb/s operation RX_CLK is 25 MHz and during 10 Mb/s this is

2.5 MHz.

Receive PMA Clock 1: In TBI mode, this 62.5Mhz clock is used in conjunction

with RXPMACLK0 to clock 10-bit TBI data into the DP83821. The rising edge of

RXPMACLK1 clocks the even-numbered bytes.

RXD7,

RXD6,

RXD5,

RXD4,

RXD3,

RXD2,

RXD1,

RXD0

166,

165,

164,

163,

160,

159,

158,

157

Gigabit Receive Data: This is a group of 8 signals, sourced from an external

PMD, that contains data aligned on byte boundaries and are driven

synchronous to the RX_CLK. RXD7 is most significant bit.

Receive Data: This is a group of 4 signals, sourced from an external PMD, that

contains data aligned on nibble boundaries and are driven synchronous to the

RX_CLK. RXD3 is the most significant bit and RXD0 is the least significant bit.

RXD7 through RXD4 are not used in this mode.

TBI Receive Data: In TBI mode, these bits are the lower 8 bits of the 10-bit TBI

Receive data.

RXDV/RXD8

167

Receive Data Valid: This indicates that the external PMD is presenting

recovered and decoded nibbles on the RXD signals, and that RX_CLK is

synchronous to the recovered data in 100 Mb/s operation. This signal will

encompass the frame, starting with the Start-of-Frame delimiter (JK) and

excluding any End-of-Frame delimiter (TR).

TBI Receive Data: In TBI mode, this is RXD8 of the 10-bit TBI Receive data.

RXER/RXD9

168

Receive Error: This signal is asserted high synchronously by the external PMD

whenever it detects a media error and RXDV is asserted in 100 Mb/s or 1000

Mb/s operation.

TBI Receive Data: In TBI mode, this is RXD9 of the 10-bit TBI Receive data.

RXEN

171

Receive Output Enable: This pin is used to disable an external PMD while the

BIOS ROM is being accessed.

TXCLK/

RXPMACLK0

155

MII Transmit Clock: A continuous clock that is sourced by the external PMD.

During 100 Mb/s operation this is 25 MHz +/- 100 ppm. During 10 Mb/s

operation this clock is 2.5 MHz +/- 100 ppm.

Receive PMA Clock 0: In TBI mode, this 62.5Mhz clock is used in conjunction

with RXPMACLK1 to clock 10-bit TBI data into the DP83821. The rising edge of

RXPMACLK0 clocks the odd-numbered bytes.

TXD7/MA15,

TXD6/MA14,

TXD5/MA13,

TXD4/MA12,

TXD3/MA11,

TXD2/MA10,

TXD1/MA9,

TXD0/MA8

152,

151,

148,

147,

146,

145,

142,

141

Gigabit Transmit Data: This is a group of 8 signals which are driven

synchronous to GTXCLK. TXD7 is the most significant bit.

Transmit Data: This is a group of 4 data signals which are driven synchronous

to the TXCLK for transmission to the external PMD. TXD3 is the most

significant bit and TXD0 is the least significant bit. TXD7 through TXD4 are not

used in this mode

TBI Transmit Data: In TBI mode, this is the lower 8 bits of the 10-bit TBI

Transmit data.

BIOS ROM Address: During external BIOS ROM access, these signals

become part of the ROM address.

TXEN/TXD8

153

Transmit Enable: This signal is synchronous to TXCLK and provides precise

framing for data carried on TXD3-0 for the external PMD. It is asserted when

TXD3-0 contains valid data to be transmitted.

TBI Transmit Data: In TBI mode, this is TXD8 of the 10-bit TBI Transmit data.

Media Independent Interface (MII) - and Gigabit Media Independent Interface (GMII).

Symbol

Pin No(s)

Direction

Description

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