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数据搜索系统，热门电子元器件搜索 |
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DP83821 数据表(PDF) 49 Page - National Semiconductor (TI) |
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DP83821 数据表(HTML) 49 Page - National Semiconductor (TI) |
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49 / 86 page  49 www.national.com 4.0 Register Set (Continued) 4.2.8 Interrupt Enable Register The Interrupt Enable Register controls the hardware INTR signal. 4.2.9 Interrupt Holdoff Register The Interrupt Holdoff Register prevents interrupt assertion for a programmed amount of time. 4.2.10 Transmit Descriptor Pointer Register This register points to the current Transmit Descriptor. If Transmit Priority Queueing is enabled, this becomes the Descriptor pointer for Priority Queue 0 (lowest priority). Tag: IER Size: 32 bits Hard Reset: 00000000h Offset: 0018h Access: Read Write Soft Reset: 00000000h bit tag description usage 31-1 unused 0 IE Interrupt Enable When set to 1, the hardware INTR signal is enabled. When set to 0, the hardware INTR signal will be masked, and no interrupts will be generated. The setting of this bit has no effect on the ISR or IMR. This provides the ability to disable the hardware interrupt to the host with a single access (eliminating the need for a read-modify-write cycle). The actual enabling of interrupts can be delayed based on the Interrupt Holdoff Register defined in the following section. Tag: IHR Size: 32 bits Hard Reset: 00000000h Offset: 001Ch Access: Read Write Soft Reset: 00000000h bit tag description usage 31-9 unused 8 IHCTL Interrupt Holdoff Control If this bit is set, the interrupt holdoff will restart when the first interrupt condition occurs and interrupts are enabled. When this bit is not set, the interrupt holdoff will start as soon as the counter is loaded and interrupts are enabled. 7-0 IH Interrupt Holdoff This register contains a counter value for use in preventing interrupt assertion for a programmed amount of time. When the ISR is read, the interrupt holdoff timer is loaded with this value. It begins to count down to 0 based on the setting of the IHCTL bit. Once it reaches 0, interrupts will be enabled. The counter value is in units of 100us. Tag: TXDP Size: 32 bits Hard Reset: 00000000h Offset: 0020h Access: Read Write Soft Reset: 00000000h bit tag description usage 31-3 TXDP Transmit Descriptor Pointer The current value of the transmit descriptor pointer. When the transmit state machine is idle, software must set TXDP to the address of a completed transmit descriptor. While the transmit state machine is active, TXDP will follow the state machine as it advances through a linked list of active descriptors. If the link field of the current transmit descriptor is NULL (signifying the end of the list), TXDP will not advance, but will remain on the current descriptor. Any subsequent writes to the TXE bit of the CR register will cause the transmit state machine to reread the link field of the current descriptor to check for new descriptors that may have been appended to the end of the list. Transmit descriptors must be aligned on an even 64-bit boundary in host memory (A2-A0 must be 0). 2-0 unused |
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