DP83821 datasheet(13/86 Pages) NSC

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3.0 Functional Description (Continued)

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3.3.3 Master Read

A Master Read operation starts with the DP83821

asserting REQN. See Figure 3-6. If GNTN is asserted

within 2 clock cycles, FRAMEN, Address, and Command

will be generated 2 clocks after REQN (Address and

FRAMEN for 1 cycle only). If GNTN is asserted 3 cycles or

later, FRAMEN, Address, and Command will be generated

on the clock following GNTN.

The device will wait for 8 cycles for the assertion of

DEVSELN. After 8 clocks without DEVSELN, the device

will issue a Master Abort by asserting FRAMEN HIGH for 1

cycle. IRDYN will be forced HIGH on the following cycle.

Both signals will become tri-state on the cycle following

their deassertion.

On the clock edge after the generation of Address and

Command, the address bus will become tri-state, and the

C/BEN bus will contain valid byte enables. On the clock

edge after FRAMEN was asserted, IRDYN will be asserted

(and FRAMEN will be deasserted if this is to be a single

read operation). On the clock where both TRDYN and

DEVSELN are detected as asserted, data will be latched in

(and the byte enables will change if necessary). This will

continue until the cycle following the deassertion of

FRAMEN.

On the clock where the second to last read cycle occurs,

FRAMEN will be forced HIGH (it will be tri-stated 1 cycle

later). On the next clock edge that the device detects

TRDYN asserted, it will force IRDYN HIGH. It, too, will be

tri-stated 1 cycle later. This will conclude the read

operation. The DP83821 will never force a wait state during

a read operation.

Figure 3-6 Master Read Operation

3.3.4 Master Write

A Master Write operation starts with the DP83821

asserting REQN. See Figure 3-7. If GNTN is asserted

within 2 clock cycles, FRAMEN, Address, and Command

will be generated 2 clocks after REQN (Address and

FRAMEN for 1 cycle only). If GNTN is asserted 3 cycles or

later, FRAMEN, Address, and Command will be generated

on the clock following GNTN.

The device will wait for 8 cycles for the assertion of

DEVSELN. After 8 clocks without DEVSELN, the device

will issue a Master Abort by asserting FRAMEN HIGH for 1

cycle. IRDYN will be forced HIGH on the following cycle.

Both signals will become tri-state on the cycle following

their deassertion.

On the clock edge after the generation of Address and

Command, the data bus will become valid, and the C/BEN

bus will contain valid byte enables. On the clock edge after

FRAMEN was asserted, IRDYN will be asserted (and

FRAMEN will be deasserted if this is to be a single read

operation).

the

clock

where

both

TRDYN

and

DEVSELN are detected as asserted, valid data for the next

cycle will become available (and the byte enables will

change if necessary). This will continue until the cycle

following the deassertion of FRAMEN.

On the clock where the second to last write cycle occurs,

FRAMEN will be forced HIGH (it will be tri-stated 1 cycle

later). On the next clock edge that the device detects

TRDYN asserted, it will force IRDYN HIGH. It, too, will be

tri-stated 1 cycle later. This will conclude the write

operation. The DP83821 will never force a wait state during

a write operation.

Addr

Data

CLK

FRAMEN

AD[31:0]

C/BEN[3:0]

REQN

GNTN

IRDYN

TRDYN

DEVSELN

PAR

DP83821 数据表(PDF) 13 Page - National Semiconductor (TI)

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