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DP83821 数据表(PDF) 8 Page - National Semiconductor (TI) |
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DP83821 数据表(HTML) 8 Page - National Semiconductor (TI) |
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8 / 86 page ![]() 8 www.national.com 2.0 Pin Descriptions (Continued) Note: DP83821 supports NMC93C46 for the eeprom interface device. MA3/EEDI 108 O EEPROM Data In: During an EEPROM access (EESEL asserted), this output is drives opcode, address, and data to an external serial EEPROM device. MD4/EEDO 101 I EEPROM Data Out: During an EEPROM access (EESEL asserted), this pin is an input used to retrieve EEPROM serial read data. This pin pad has an internal weak pull up. JTAG Interface Symbol Pin No(s) Direction Description TCK 178 I Test Clock TDI 181 I Test Data Input TDO 180 O Test Output TMS 179 I Test Mode Select TRSTN 177 I Test Reset Supply Pins Symbol Pin No(s) Direction Description COREVDD 89, 116, 174, 206 S Mac/BIU digital core VDD - connect to Aux 1.8V supply VDD COREVSS 88, 115, 173, 205 S Mac/BIU digital core VSS. OSCVDD 123 S Oscillator VDD - connect to Aux 1.8V supply VDD OSCVSS 120 S Oscillator VSS. PCIVDD 187, 201, 7, 20, 30, 40, 51, 60, 71, 80 S PCI IO VDD - connect to PCI bus 3.3V VDD PCIVSS 182, 196, 3, 16, 27, 36, 46, 56, 66, 76 S PCI IO VSS VDDIO, AVDD 100, 111, 136, 144, 150, 162, 125 S Misc. IO VDD, Analog VDD - connect to Aux 3.3V supply VDD VSSIO, AVSS 99, 110, 135, 143, 149, 161, 124 S Misc. IO VSS, Analog VSS No Connects Symbol Pin No(s) Direction Description Reserved 90, 117, 118, 119, 126 These pins are reserved and cannot be connected to any external logic or net. Serial EEPROM Interface Symbol Pin No(s) Direction Description |
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