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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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DP83821 数据表(PDF) 75 Page - National Semiconductor (TI) |
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DP83821 数据表(HTML) 75 Page - National Semiconductor (TI) |
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75 / 86 page  5.0 DC and AC Specifications (Continued) 75 www.national.com 5.2.3 Power On Reset (PCI Active) Note 1: Minimum reset complete time is a function of the PCI, transmit, and receive clock frequencies. Note 2: Minimum access after reset is dependent on PCI clock frequency. Accesses to DP83821 during this period will be ignored. Note 3: EE is disabled for non power on reset. 5.2.4 Non Power On Reset Note 4: Minimum reset complete time is a function of the PCI, transmit, and receive clock frequencies. Number Parameter Min Typ Units 5.2.3.1 RSTN Active Duration from PCICLK stable 1ms 5.2.3.2 Reset Disable to 1st PCI Cycle EE Enabled EE Disabled 2000 1 us us Number Parameter Min Typ Units 5.2.4.1 RSTN to Output Float 40 ns T2 1st PCI Cycle Reset Complete Power Stable RSTN PCICLK T1 1st PCI Cycle RSTN T1 Output |
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