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CDCDB2000

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SNAS787 – NOVEMBER 2019

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Table 5. OECR1 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

4

Output Enable, CK17

R/W

1h

This bit controls the output enable signal for output channel

CK17_P/CK17_N.

0h = Output Disabled

1h = Output Enabled

3

Output Enable, CK16

R/W

1h

This bit controls the output enable signal for output channel

CK16_P/CK16_N.

0h = Output Disabled

1h = Output Enabled

2-0

RESERVED

R

0h

Reserved

7.6.1.2 OECR2 Register (Address = 1h) [reset = FFh]

OECR2 is shown in Table 6.

Return to the Summary Table.

The OECR2 register contains bits that enable or disable individual output clock channels [7:0]

Table 6. OECR2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

Output Enable, CK7

R/W

1h

This bit controls the output enable signal for output channel

CK7_P/CK7_N.

0h = Output Disabled

1h = Output Enabled

6

Output Enable, CK6

R/W

1h

This bit controls the output enable signal for output channel

CK6_P/CK6_N.

0h = Output Disabled

1h = Output Enabled

5

Output Enable, CK5

R/W

1h

This bit controls the output enable signal for output channel

CK5_P/CK5_N.

0h = Output Disabled

1h = Output Enabled

4

Output Enable, CK4

R/W

1h

This bit controls the output enable signal for output channel

CK4_P/CK4_N.

0h = Output Disabled

1h = Output Enabled

3

Output Enable, CK3

R/W

1h

This bit controls the output enable signal for output channel

CK3_P/CK3_N.

0h = Output Disabled

1h = Output Enabled

2

Output Enable, CK2

R/W

1h

This bit controls the output enable signal for output channel

CK2_P/CK2_N.

0h = Output Disabled

1h = Output Enabled

1

Output Enable, CK1

R/W

1h

This bit controls the output enable signal for output channel

CK1_P/CK1_N.

0h = Output Disabled

1h = Output Enabled

0

Output Enable, CK0

R/W

1h

This bit controls the output enable signal for output channel

CK0_P/CK0_N.

0h = Output Disabled

1h = Output Enabled