9

CDCDB2000

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SNAS787 – NOVEMBER 2019

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Copyright © 2019, Texas Instruments Incorporated

Electrical Characteristics (continued)

VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(6)

Measured from rising edge of any CKx output to any other CKx output.

Skew between outputs

ps

Additive jitter

DB2000QL filter

0.08

ps, rms

Additive jitter for PCIe5

PCIe5.0 filter

0.03

ps, rms

Additive jitter for PCIe4

PLL BW = 2 - 5 MHz; CDR =

10 MHz

Input clock

slew rate

≥ 1.8 V/ns

0.08

ps, rms

Additive jitter for PCIe3

Input clock

slew rate

≥ 0.6 V/ns

0.15

ps, rms

Additive jitter for PCIe2

PCIe2 filter

0.2

ps, rms

Additive jitter for PCIe1

PCIe1 filter

5

ps, rms

Additive jitter

to 20 MHz integration bandwidth.

155

fs, rms

SMBUS INTERFACE, SIDE-BAND INTERFACE, OEx#, CKPWRGD_PD#, SBEN

High-level input voltage

2.0

V

Low-level input voltage

0.8

Input leakage current

With internal pull up/pull-down

–30

30

uA

Without internal pull up/pull-

down

–5

5

Input capacitance

4.5

pF

Output capacitance

4.5

pF

3-LEVEL DIGITAL INTERFACE (SA_0, SA_1)

High-level input voltage

2.4

V

Mid level input voltage

1.3

1.8

Low-level input voltage

0.9

Input high current

-10

10

uA

Input leakage current

With internal pull up/pull-down

–30

30

6.6 Timing Requirements

VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

MIN

NOM

MAX

UNIT

SMBUS-COMPATIBLE INTERFACE TIMING

SMBus operating frequency

10

100

kHz

Bus free time between STOP and

START

4.7

µs

START condition hold time

4

START condition setup time

4.7

STOP condition setup time

4

SMBDAT hold time

300

ns

SMBDAT setup time

250

Detect SMBCLK low timeout

25

35

ms

SMBCLK low period

4.7

µs

SMBCLK high period

4

50

Cumulative clock low extend time

25

ms