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CDCDB2000NPPR 数据表(PDF) 3 Page - Texas Instruments

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部件名 CDCDB2000NPPR
功能描述  CDCDB2000 DB2000QL-Compliant 20-Output Clock Buffer for PCIe Gen 1 to Gen 5
PDF  33 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

CDCDB2000NPPR 数据表(HTML) 3 Page - Texas Instruments

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DAP = GND
CK17
_P
CK17
_N
CK18
_P
CK18
_N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD
SBEN
CK16
_N
CK16
_P
CK19
_P
CK19
_N
CLKIN
_P
CLKIN
_N
VDD
_A
CK0
_P
CK0
_N
CK1
_P
CK1
_N
VDD
CK2
_P
CK2
_N
CK3
_P
CK3
_N
SMB
DAT
SMB
CLK
CK4
_P
CK4
_N
CK5
_P
CK5
_N
CK6
_P
CK6
_N
NC
VDD
OE6#
CLK
OE5#
DATA
CK7
_P
CK7
_N
CK8
_P
CK8
_N
CK9
_P
CK9
_N
OE9#
CK10
_P
CK10
_N
NC
NC
OE7#
OE8#
NC
NC
OE11#
OE10#
SHFT
_LD#
VDD
CK11
_P
CK11
_N
CK12
_P
CK12
_N
OE12#
CK13
_P
CK13
_N
NC
SADR
1
NC
VDD
SADR
0
CK14
_P
CK15
_P
CK15
_N
CK14
_N
CKPW
RGD
_PD#
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
3
CDCDB2000
www.ti.com
SNAS787 – NOVEMBER 2019
Product Folder Links: CDCDB2000
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
5 Pin Configuration and Functions
CDCDB2000 NPP Package
80-Pin TLGA
Top View
Pin Functions
PIN
I/O TYPE
DESCRIPTION
NAME
NO.
INPUT CLOCK
CLKIN_P
G1
I
LP-HCSL differential clock input. Typically connected directly to the differential
output of clock source.
CLKIN_N
H1
I
OUTPUT CLOCKS
CK0_P
J1
O
LP-HCSL differential clock output of channel 0. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK0_N
K1
O
CK1_P
L1
O
LP-HCSL differential clock output of channel 1. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK1_N
M1
O
CK2_P
M2
O
LP-HCSL differential clock output of channel 2. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK2_N
M3
O
CK3_P
M4
O
LP-HCSL differential clock output of channel 3. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK3_N
M5
O
CK4_P
M7
O
LP-HCSL differential clock output of channel 4. Typically connected directly to
PCIe differential clock input. If unused, the pins can be left no connect.
CK4_N
M8
O



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