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CDCDB2000

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SNAS787 – NOVEMBER 2019

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Table 8. OERDBK Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

2

OE7# State

R

0h

This bit reports the logic level present on the OE7# pin.

1

OE6# State

R

0h

This bit reports the logic level present on the OE6# pin.

0

OE5# State

R

0h

This bit reports the logic level present on the OE5# pin.

7.6.1.5 SBRDBK Register (Address = 4h) [reset = 1h]

SBRDBK is shown in Table 9.

Return to the Summary Table.

The SBRDBK register contains a bit that report the current state of the SBEN input pin.

Table 9. SBRDBK Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

RESERVED

R

0h

Reserved

0

SBEN State

R/W

1h

This bit reports the logic level present on the SBEN pin.

7.6.1.6 VDRREVID Register (Address = 5h) [reset = X]

VDRREVID is shown in Table 10.

Return to the Summary Table.

The VDRREVID register contains a vendor identification code and silicon revision code.

Table 10. VDRREVID Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

Revision Code[3:0]

R

X

Silicon revision code.

Silicon revision code bits

[3:0] map to register bits

[7:4] directly.

3-0

Vendor ID[3:0]

R

X

Vendor identification code.

Vendor ID bits

[3:0] map to register bits

[3:0] directly.

7.6.1.7 DEVID Register (Address = 6h) [reset = X]

DEVID is shown in Table 11.

Return to the Summary Table.

The DEVID register contains a device identification code.

Table 11. DEVID Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

Device ID[7:0]

R

X

Device ID code.

Device ID bits[7:0] map to register bits[7:0] directly.

7.6.1.8 BTRDCNT Register (Address = 7h) [reset = 8h]

BTRDCNT is shown in Table 12.

Return to the Summary Table.

The BTRDCNT register allows configuration of the number of bytes that will be read back from the SMBus

interface on an issued read command.