Recommended ground vias

Vias to escape

inside pins

All CKx pairs routed

differentially

27

CDCDB2000

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SNAS787 – NOVEMBER 2019

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10 Layout

10.1 Layout Guidelines

The following section provides the layout guidelines to ensure good thermal performance and power supply

connections for the CDCDB2000.

10.2 Layout Examples

Figure 12 and Figure 13 are PCB layout examples that show the application of thermal design practices and a

low-inductance ground connection between the device DAP and the PCB.

The CDCDB2000 has 85-Ω differential output impedance LP-HCSL format drivers. All transmission lines

connected to CKx pins should be 85-Ω differential impedance, 42.5-Ω single-ended impedance to avoid

reflections and increased radiated emissions. Take care to eliminate or reduce stubs on the transmission lines.

Figure 12. PCB Layout Example for CDCDB2000, Top Layer