10

ATSAM9743

1773B–DRMSD–11/02

Timing

Diagrams

All timing conditions: V

except X2. All timings refer to t

t

External Memory

(16 bits)

Figure 4. External ROM/RAM (16 bits)

WCS0

WOE

WD[15:0]

WA[20:0]

WCS1

WWE

Table 8. Parameters for External Memory Read/Write Cycle (16 bits)

Symbol

Parameter

Min

Typ

Max

Unit

t

CSDV

Access time from WCSx low

5 x t

ns

t

RWDV

Access time from WOE, WWE low

3 x t

ns

Access time from address valid

ns

t

RW

WOE, WWE pulse width

4 x t

CK

ns

t

RWHCSH

WCSx high from rising WOE or WWE

10

ns

Address valid after rising WOE or WWE

10

ns

t

RWDX

Data hold time from rising WOE or WWE

10

6 x t

CK

ns