16

ATSAM9743

1773B–DRMSD–11/02

On Board Flash

Program/Debug

Mode

TEST1 = 0, TEST0 = 1:

In this mode, the P16 program starts in the built-in debug ROM. All ports are set to input mode

with a weak pull-down, except P3.10 and P3.11 which are set to MIDI_IN and MIDI_OUT,

respectively.

If TEST2 = 0, the baud rate is set to the MIDI standard (31250 baud). If TEST2 = 1 the baud

rate is set to 57600 baud. This later setting is useful when Flash programming time is a pro-

duction cost issue.

Programming the built-in Flash, or debugging a P16 program, occurs exclusively through the

MIDI_IN and MIDI_OUT pins, which means that any firmware can be debugged except the

MIDI part of the firmware (note that as the ATSAM9743 is compatible with the ATSAM97xx

series, it is easy to debug the MIDI with another development board such as 97PNP2).

MIDI_IN Commands

The following is only given for information purposes, as the CV9743 CodeView debugger

takes care of all the protocol handling between a PC and the ATSAM9743 target board.

Commands are received through MIDI_IN, all commands except GO and GR are acknowl-

edged. A new command should not be sent until the acknowledge from a previous command

is received.

Note that the commands are compatible with the standard Debug program from the

ATSAM97xx series.

The first command sent to the ATSAM9743 after reset should be INIT (0F0H).

Table 12. Parameters for MIDI_IN/MIDI_OUT Commands and Answers

MIDI_IN

Command

Byte

Parameters

MIDI_OUT

Answer

Description

INIT 0F0H

–

Ack (0ACH)

Establish link. This should be the first command sent after reset.

RDIRAM 00H

ad

dl, dh

Read P16 IRAM at ad

WRIRAM 01H

ad, dl, dh

Ack (0ACH)

Write dh/dl at P16 IRAM address ad

RDXTMEM

02H

adl, adh, pl, ph

dl, dh

Read word of P16 external memory at address ph/pl:adh/adl. Note that from a

P16 point of view, the built-in Flash and 2K x 16 SRAM are external memory.

WRXTMEM

03H

adl, adh, pl,

ph, dl, dh

Ack (0ACH)

Write dh/dl word of data to P16 external memory at address ph/pl:adh/adl. If

the address falls into the Flash range, then Flash-programming algorithm is

applied. Ack is returned after the write is completed.

RDIO 04H

ioad

dl, dh

Read P16 I/O at ioad

WRIO 05H

ioad, dl, dh

Ack (0ACH)

Write dh/dl at I/O address ioad

RDSAML 06H

samadl,

samadh

dl, dh

Read low word of synthesis DSP RAM at samadh/samadl

RDSAMH 07H

samadl,

samadh

dl, dh

Read high word of synthesis DSP RAM at samadh/samadl

WRSAM 08H

samadl,

samadh, d0,

d1, d2, d3

Ack (0ACH)

Write 32 bits (d3/d2/d1/d0) of data to Synthesis DSP RAM at address

samadh/samadl

GO 09H

adl, adh

See note

Jump to adh/adl (start firmware)

GR 0AH

Dummy

See note

Restore firmware context

RDBLOCK

0BH

adl, adh, pl,

ph, sizel, sizeh

2*size bytes

Read size words of external memory starting at address ph/pl/adh/adl