3

ATSAM9743

1773B–DRMSD–11/02

Internal

Architecture

The highly-integrated architecture of the ATSAM9743 combines a specialized high-perfor-

mance RISC-based digital signal processor (DSP) and a general-purpose 16-bit CISC-based

control processor (P16). An on-chip memory management unit (MMU) allows the DSP and the

control processor to share an internal 24K x 16 Flash memory, 2K x 16 RAM, as well as

optional external ROM and/or RAM memory devices configured through the Ports & Flash

control registers.

An intelligent peripheral I/O interface function handles other I/O interfaces, such as the on-chip

MIDI UART and three timers, with minimum intervention from the control processor.

Four 16-bit I/O ports can have their bits individually configured as inputs or outputs, they can

also be assigned alternate functions such as external memory access (address, data and con-

trol signals), 8-bit parallel MIDI port, serial MIDI_IN/MIDI_OUT, and additional digital audio-

in/out.

See Table 2 on page 5 and Table 3 on page 6 for details.

Figure 2. Diagram of the Internal Architecture of the ATSAM9743

DSP Engine

The DSP engine operates on a frame-timing basis with the frame subdivided into 64 process

slots. Each process is itself divided into 16 microinstructions known as “algorithms”. Up to 32

DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the device to be pro-

grammed for a number of audio signal generation/processing applications.

The DSP engine is capable of generating 64 simultaneous voices using algorithms such as

wavetable synthesis with interpolation, alternate loop and 24 dB resonant filtering for each

voice. Slots may be linked together (ML RAM) to allow implementation of more complex syn-

thesis algorithms.

A typical musical instrument application will use a little more than half the capacity of the DSP

engine for synthesis, thus providing state-of-the-art 38-voice synthesis polyphony. The

remaining processing power may be used for typical functions like reverberation, chorus, sur-

round effect, equalizer, etc.

Frequently accessed DSP parameter data are stored in five banks of on-chip RAM memory.

Sample data, which is accessed relatively infrequently, can be stored in the built-in Flash

P0[15:0]

P1[15:0]

P2[15:0]

P3[15:0]

CLBD

WSBD

DABD0

X1, X2, LFT

RESET

PDWN

CKOUT

Clock

&

PLL

P16

Processor

256 x 16 RAM

1K x 16 ROM

MIDI UART

3 x Timers

Standard ATSAM97xx

Control Registers

64-Slot DSP

with

Alogrithms in RAM

Memory

Manager

Unit

Flash

24K x 16

RAM

2K x 16

Ports & Flash

Control Registers