5

ATSAM9743

1773B–DRMSD–11/02

Pin Description

Pins by Function

Note:

Power supply decoupling: Like all high speed HCMOS ICs, proper decoupling is mandatory for reliable operation and RFI reduc-

tion. The recommended decoupling is 100 nF at each corner of the IC with an additional 10 µFT bulk capacitor close to the X1,

X2 pins.

Note:

Pin names exhibiting an overbar (PDWN for example) indicate that the signal is active low.

Table 1. Power Supply

Pin Name

Pin Number

Type

Function

GND

5, 10, 18, 22, 33, 45, 47, 59, 62, 75, 88, 99

PWR

Digital Ground: All pins should be connected to a

ground plane

VC3

3, 11, 21, 27, 61

PWR

Core Power Supply, 3V to 3.8V:

All pins should be connected

VCC

17, 31, 46, 57, 73, 87, 100

PWR

I/O Power Supply, 3V to 5.5V:

All pins should be connected to a VCC plane

Table 2. Single Function Pins

Pin Name

Pin Number

Type

Function

CLBD

26

OUT

External DAC serial bit clock

WSBD

37

OUT

External DAC left/right clock

DABD0

35

OUT

External DAC serial stereo audio data

P3.12 - P3.14

81, 23, 24

Programmable

General purpose I/O

X1

13

IN

Crystal connection, or external clock input at

256*Fs, Fs being the sampling frequency. When

used as an input, a 330 ohms serial resistor

should be inserted. Typical crystal frequency is

8 MHz (Fs = 32 kHz)

X2

14

OUT

Other end of crystal connection. Cannot be used

to drive external circuitry.

CKOUT

95

OUT

Buffered X2 output, can be used to drive external

circuits, such as Sigma/Delta DACs

LFT

12

Analog

Built-in PLL compensation filter input

RESET

15

IN

Master reset, active low, has built-in Schmitt

trigger.

PDWN

16

IN

Power down, active low

TEST[2:0]

42 - 44

IN

Test pins. Should be grounded for normal

operation.

TEST0 is used to start the built-in debugger.

In this case TEST2 specifies the communication

baud rate.