18

ATSAM9743

1773B–DRMSD–11/02

Flash Program

and Test

Registers

Three additional write I/O registers and two read I/O registers are implemented for the built-in

Flash program and test, as follows.

FADDTEST Register

Address 0020:080AH

(Read/Write)

This 15-bit register provides the addtest<14:0> address bus to the Flash block. This is the

address register when programming the Flash.

FDI Register

Address 0020:080BH

(Read/Write)

This 16-bit register provides the di<15:0> data bus to the Flash block. This is the data register

when programming the Flash.

FCOMMAND Register

Address 0020:0809H

(Cleared at RESET time)

(Read/Write)

•

RSTT,CEN, WE, PAGEM, PAGE1,TM5–TM0: Signals sent to corresponding Flash block inputs. These signals, with

proper timing, provide Flash programming.

FSTATUS Register

Address 0020:0809H

(Read-only)

•

RDYBSYN and DOUTEN: These Flash signals provide write-progress monitoring respectively.

•

TEST0–TEST2: Input pins, respectively.

FDOTEST Register

(Read-only)

Reads the dotest <15:0> Flash data output bus for test modes.

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RSTT

CEN

WE

PAGEM PAGE1

TM5

TM4

TM3

TM2

TM1

TM0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

X

X

X

X

TEST2 TEST1 TEST0

XXXXXX

DOUTEN RDYBSYN