TDA7786 datasheet(13/54 Pages) STMICROELECTRONICS

13 / 54 page

DocID026122 Rev 5

13/54

TDA7786, TDA7786M

Function description

2.6

IF A/D converters

A high performance IQ-IFADC converts the IF signal to the digital domain for subsequent

digital signal processing.

Two fully differential, continuous-time Sigma-Delta (Σ∆) IF-ADCs are used for both the 'I'

path and the 'Q' path. For each IFADC, two fully differential input nodes are fed with an input

signal having a bandwidth up to 325 kHz. This fully differential design provides good

suppression of even-order harmonics. For complex filtering, the input signals of the 'I' path

and the 'Q' path have a 90 degree phase shift. The IFADC sampling frequency is 36.48

MHz.

2.7

Audio D/A converters

A CD-quality (>100dB DR) stereo DAC provides the left/right audio signals after IF

processing and stereo-decoding by the DSP. In presence of an external HD Radio™

decoder the DAC delivers the high quality audio resulting from the decoding of the

HD Radio™ transmissions.

2.8

VCO

The VCO is fully integrated without any external tuning component. It covers all the FM

frequency bands including EU, US, Japan, East-Europe, Weather-Band and the AM bands

including LW, MW and SW. Its center frequency is approximately 2.7 GHz.

2.9

PLL

2.9.1

Tuner PLL

The very high-speed tuning PLL is able to settle within about 100 µs for fast RDS

applications. The frequency step can be as low as 5 kHz in FM and 500 Hz in AM.

2.10

Crystal oscillator

The device works with a 36.48 MHz fundamental tone crystal. The oscillator block diagram

is shown in Figure 3. On the PCB the crystal must be connected as close as possible to the

chip oscillator input and output pins of the chip. The internal load capacitance together with

pin and pad capacitance is optimized for fundamental tone crystal units at 36.48 MHz. It is

not recommended to put any additional external load capacitors. By suitably configuring pin

#9 (CK_SEL), the device can be operated as either a clock master or a clock slave. If pin 9

is left open or tied to GND, the device is configured as clock master (typical operation

mode). In case the device is configured as clock slave, pin 9 needs to be connected to 5 V.

Then the crystal oscillator is switched off and the device expects a crystal equivalent signal

on the OSCout/OSCin pins.

TDA7786 数据表(PDF) 13 Page - STMicroelectronics

TDA7786 数据表(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

数据表下载