TDA7786 datasheet(23/54 Pages) STMICROELECTRONICS

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TDA7786, TDA7786M

Function description

2.17.2

I2C bus protocol

The I2C communication requires two signals: clock (SCL) and data (SDA - bidirectional).

The protocol requires an acknowledge signal after any 8-bit transmission.

A "write" communication example is shown in the figure below, for an unspecified number of

data bytes (see the relevant technical documentation for frame structure description):

Figure 11. I2C "write" sequence

The sequence consists of the following phases:

START: SDA line transitioning from H to L with SCL fixed H. This indicates that a new

transmission is starting;

DATA LATCHING: on the rising SCL edge. The SDA line can vary only when SCL is

low (otherwise its transitions are interpreted as either a START or a STOP transition);

ACKNOWLEDGE: on the 9th SCL pulse the microprocessor keeps the SDA line H, and

the TDA7786x pulls it down in case the communication has been successful. Lack of

the acknowledge pulse generation from the TDA7786x indicates a communication

failure; the chip-address byte must be sent at the beginning of the transmission. The

value can be 0xC2 or 0xC8 (according to the mode chosen at start-up) for "write"; as

many data bytes as needed can follow the address before the communication is

terminated. See the next section for details on the frame format;

STOP: SDA line transitioning from L to H with SCL H. This signifies the end of the

transmission.

Dashed lines represent transmissions from the TDA7786x to the microprocessor. A

communication example is shown in the figure below, for an unspecified number of data

bytes (see later on for frame structure description):

Figure 12. I2C "read" sequence

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