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TLV9152SIRUGR 数据表(PDF) 34 Page - Texas Instruments |
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TLV9152SIRUGR 数据表(HTML) 34 Page - Texas Instruments |
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34 / 63 page ![]() NC ±IN +IN V± V+ OUTPUT NC NC VS+ VS± GND Ground (GND) plane on another layer VOUT VIN GND Run the input traces as far away from the supply lines as possible RF RG Place components close to device and to each other to reduce parasitic errors Use low-ESR, ceramic bypass capacitor GND Use a low-ESR, ceramic bypass capacitor + VIN VOUT RG RF 34 TLV9151, TLV9152, TLV9154 SBOS986B – OCTOBER 2019 – REVISED MAY 2020 www.ti.com Product Folder Links: TLV9151 TLV9152 TLV9154 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated 10.2 Layout Example Figure 53. Schematic Representation Figure 54. Operational Amplifier Board Layout for Noninverting Configuration |
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