TLV9152SIRUGR datasheet(10/63 Pages) TI

10 / 63 page

TLV9151, TLV9152, TLV9154

SBOS986B – OCTOBER 2019 – REVISED MAY 2020

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Product Folder Links: TLV9151 TLV9152 TLV9154

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(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be

current limited to 10 mA or less.

(3)

Short-circuit to ground, one amplifier per package.

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

Supply voltage, VS = (V+) – (V–)

Signal input pins

Common-mode voltage (2)

(V–) – 0.5

(V+) + 0.5

Differential voltage (2)

VS + 0.2

Current (2)

–10

Output short-circuit (3)

Continuous

Operating ambient temperature, TA

–55

150

°C

Junction temperature, TJ

150

°C

Storage temperature, Tstg

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2000

Charged device model (CDM), per JEDEC specification JESD22-C101 (2)

±1000

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

MAX

UNIT

Supply voltage, (V+) – (V–)

2.7

Input voltage range

(V–) – 0.1

(V+) + 0.1

VIH

High level input voltage at shutdown pin (amplifier enabled)

1.1

(V+)

VIL

Low level input voltage at shutdown pin (amplifier disabled)

(V–)

0.2

Specified temperature

–40

125

°C

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2)

This package option is preview for TLV9151.

6.4 Thermal Information for Single Channel

THERMAL METRIC (1)

TLV9151, TLV9151S

UNIT

DBV (2)

(SOT-23)

DCK (2)

(SC70)

DRL (2)

(SOT-553)

5 PINS

6 PINS

5 PINS

6 PINS

RθJA

Junction-to-ambient thermal resistance

185.7

167.8

202.6

TBD

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

108.2

107.9

101.5

TBD

°C/W

RθJB

Junction-to-board thermal resistance

54.5

49.7

47.8

TBD

°C/W

ψJT

Junction-to-top characterization parameter

31.2

33.9

18.8

TBD

°C/W

ψJB

Junction-to-board characterization parameter

54.2

49.5

47.4

TBD

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

TBD

°C/W

TLV9152SIRUGR 数据表(PDF) 10 Page - Texas Instruments

TLV9152SIRUGR 数据表(HTML) 10 Page - Texas Instruments

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TLV9152SIRUGR 数据表(PDF) 10 Page - Texas Instruments

TLV9152SIRUGR 数据表(HTML) 10 Page - Texas Instruments

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