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TLV9152SIRUGR 数据表(PDF) 19 Page - Texas Instruments

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部件名 TLV9152SIRUGR
功能描述  TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp
PDF  63 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TLV9152SIRUGR 数据表(HTML) 19 Page - Texas Instruments

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Cap Load (pF)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
10
20
30
40
50
60
C009
Time (20us/div)
C016
Input
Output
Cap Load (pF)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
10
20
30
40
50
60
C007
RISO = 0 , Positive Overshoot
RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot
Cap Load (pF)
0
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
0
10
20
30
40
50
60
70
80
C008
RISO = 0 , Positive Overshoot
RISO = 0 , Negative Overshoot
RISO = 50 , Positive Overshoot
RISO = 50 , Negative Overshoot
Temperature (°C)
-40
-20
0
20
40
60
80
100
120
140
115
120
125
130
135
140
D023
VS = 4 V
VS = 16 V
Frequency (Hz)
150
200
250
300
350
400
450
500
550
600
650
700
100
1k
10k
100k
1M
10M
C013
19
TLV9151, TLV9152, TLV9154
www.ti.com
SBOS986B – OCTOBER 2019 – REVISED MAY 2020
Product Folder Links: TLV9151 TLV9152 TLV9154
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Typical Characteristics (continued)
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 10 pF (unless otherwise noted)
Figure 25. Open-Loop Voltage Gain vs Temperature (dB)
Figure 26. Open-Loop Output Impedance vs Frequency
G = –1, 10-mV output step
Figure 27. Small-Signal Overshoot vs Capacitive Load
G = 1, 10-mV output step
Figure 28. Small-Signal Overshoot vs Capacitive Load
Figure 29. Phase Margin vs Capacitive Load
VIN = ±8 V; VS = VOUT = ±17 V
Figure 30. No Phase Reversal



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