USB334X datasheet(28/92 Pages) MICROCHIP

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USB334x

DS00002646A-page 28

 2009-2018 Microchip Technology Inc.

5.4

Crystal Reference Support (USB3343 only)

The USB3343 provide support for a 26 MHz crystal to provide the reference frequency required by the device in place

of a clock oscillator. The crystal should be connected to the REFCLK/XI and XO pins as shown in Figure 8-2. If a 26 MHz

clock oscillator is used in place of a crystal, it should be driven into the REFCLK/XI pin, and the XO pin should be left

floating.

Proper care should be taken to ensure that a crystal is selected with appropriate power dissipation characteristics.

5.5

Integrated Low Jitter PLL

The USB334x uses an integrated low jitter phase locked loop (PLL) to provide a clean 480 MHz clock required for HS

USB signal quality. This clock is used by the PHY during both transmit and receive. The USB334x PLL requires an accu-

rate frequency reference to be driven on the REFCLK pin.

5.5.1

REFCLK FREQUENCY SELECTION

The USB334x PLL is designed to operate in one of two reference clock modes. In the first mode, the 60 MHz ULPI clock

is driven on the REFCLK pin. In the second mode a reference clock is driven on the REFCLK pin. The Link is driving

the ULPI clock, in the first mode, and this is referred to as ULPI Clock Input Mode. In the second mode, the USB334x

generates the ULPI clock, and this is referred to as ULPI Clock Output Mode.

During start-up, the USB334x monitors the CLKOUT pin. If a connection to VDD18 (USB3341, USB3346, and

USB3347) or VDDIO (USB3343) is detected, the USB334x is configured for a 60 MHz ULPI reference clock driven on

the REFCLK pin. Section 5.5.1.1, "ULPI Clock Input Mode (60 MHz REFCLK Mode)," on page 28 and Section 5.5.1.2,

"ULPI Clock Output Mode," on page 29 describe how to configure the USB334x for either ULPI Clock Input Mode or

ULPI Clock Output Mode.

5.5.1.1

ULPI Clock Input Mode (60 MHz REFCLK Mode)

When using ULPI Clock Input Mode, the Link must supply the 60 MHz ULPI clock to the USB334x. In this mode the

60 MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin is tied high to VDD18 (USB3341, USB3346,

and USB3347) or VDDIO(USB3343).

After the PLL has locked to the correct frequency, the USB334x will de-assert DIR and the Link can begin using the

ULPI interface. The USB334x will start the clock within the time specified in Table 4-3. For Host applications, the ULPI

AutoResume bit should be enabled. This is described in Section 6.4.1.4, "Host Resume K," on page 53.

FIGURE 5-3:

CONFIGURING THE USB334X FOR ULPI CLOCK INPUT MODE (60 MHZ)

CLKOUT

REFCLK

SMSC PHY

Clock

Source

To PLL

Link

ULPI Clk Out

Reference Clk In

VDD18/

VDDIO

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