USB334X datasheet(44/92 Pages) MICROCHIP

44 / 92 page

USB334x

DS00002646A-page 44

 2009-2018 Microchip Technology Inc.

in the following sections while the descriptions of the asynchronous modes are described in Section 6.5, "Low Power

Mode," on page 55, Section 6.6, "Full Speed/Low Speed Serial Modes," on page 58, and Section 6.7, "Carkit Mode," on

page 59.

6.1.2

ULPI INTERFACE TIMING IN SYNCHRONOUS MODE

The control and data timing relationships are given in Figure 6-2 and Table 4-4. All timing is relative to the rising clock

edge of the 60 MHz ULPI Clock.

6.2

ULPI Register Access

The following section details the steps required to access registers through the ULPI interface. At any time DIR is low

the Link may access the ULPI registers set using the Transmit Command byte. The ULPI registers retain their contents

when the PHY is in Low Power Mode, Full Speed/Low Speed Serial Mode, or Carkit Mode.

6.2.1

TRANSMIT COMMAND BYTE (TX CMD)

A command from the Link begins a ULPI transfer from the Link to the USB334x. Before reading a ULPI register, the Link

must wait until DIR is low, and then send a Transmit Command Byte (TX CMD) byte. The TX CMD byte informs the

USB334x of the type of data being sent. The TX CMD is followed by a data transfer to or from the USB334x. Table 6-2

gives the TX command byte (TX CMD) encoding for the USB334x. The upper two bits of the TX CMD instruct the PHY

as to what type of packet the Link is transmitting.

FIGURE 6-2:

ULPI SINGLE DATA RATE TIMING DIAGRAM IN SYNCHRONOUS MODE

60MHz ULPI -

CLK

Control In -

STP

Data In -

DATA[7:0]

Control Out -

DIR, NXT

Data Out -

DATA[7:0]

TSC

TSD

THC

THD

TDC

TDD

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