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ADAR2001ACCZ 数据表(PDF) 29 Page - Analog Devices |
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ADAR2001ACCZ 数据表(HTML) 29 Page - Analog Devices |
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29 / 39 page  Data Sheet ADAR2001 Rev. 0 | Page 29 of 39 Addr Name Bits Bit Name Description Reset Access 0x045 TX_EN1_SPI 7 CH1_RDY_SPI SPI Mode Channel 1 Ready Enable 0x0 R/W 6 CH1_ACT_SPI SPI Mode Channel 1 Active Enable 0x0 R/W 5 CH2_RDY_SPI SPI Mode Channel 2 Ready Enable 0x0 R/W 4 CH2_ACT_SPI SPI Mode Channel 2 Active Enable 0x0 R/W 3 CH3_RDY_SPI SPI Mode Channel 3 Ready Enable 0x0 R/W 2 CH3_ACT_SPI SPI Mode Channel 3 Active Enable 0x0 R/W 1 CH4_RDY_SPI SPI Mode Channel 4 Ready Enable 0x0 R/W 0 CH4_ACT_SPI SPI Mode Channel 4 Active Enable 0x0 R/W 0x046 TX_EN2_SPI [7:3] RESERVED Reserved 0x0 R 2 SPLT1_EN_SPI SPI Mode Active Splitter1 Enable 0x0 R/W 1 SPLT12_EN_SPI SPI Mode Channel 1 to Channel 2 Active Splitter Enable 0x0 R/W 0 SPLT34_EN_SPI SPI Mode Channel 3 to Channel 4 Active Splitter Enable 0x0 R/W 0x047 MULT_EN_SPI 7 RESERVED Reserved 0x0 R 6 RFAMP_EN_SPI SPI Mode RF Amplifier Enable 0x0 R/W 5 MULT_LOW_RDY_SPI SPI Mode Low Band Ready Enable 0x0 R/W 4 MULT_LOW_ACT_SPI SPI Mode Low Band Active Enable 0x0 R/W 3 MULT_MID_RDY_SPI SPI Mode Mid Band Ready Enable 0x0 R/W 2 MULT_MID_ACT_SPI SPI Mode Mid Band Active Enable 0x0 R/W 1 MULT_HIGH_RDY_SPI SPI Mode High Band Ready Enable 0x0 R/W 0 MULT_HIGH_ACT_SPI SPI Mode High Band Active Enable 0x0 R/W 0x048 MULT_PASS_SPI 7 BPF_SPI SPI Mode BPF Select 0x0 R/W 6 PA_NOTCH_SPI SPI Mode Notch Filter Select 0x0 R/W 5 RESERVED Reserved 0x0 R [4:0] ATTN_SPI SPI Mode Attenuator Setting 0x0 R/W 0x049 DET_ENABLES [7:4] RESERVED Reserved 0x0 R 3 CH4_DET_EN Enables Channel 4 Power Detector 0x0 R/W 2 CH3_DET_EN Enables Channel 3 Power Detector 0x0 R/W 1 CH2_DET_EN Enables Channel 2 Power Detector 0x0 R/W 0 CH1_DET_EN Enables Channel 1 Power Detector 0x0 R/W 0x04A ADC_CTRL 7 ADC_CLKFREQ_SEL ADC Clock Frequency Selection 0x0 R/W 6 ADC_EN Turns on Comparator and Resets State Machine 0x0 R/W 5 CLK_EN Turns on Clock Oscillator 0x0 R/W 4 ST_CONV Pulse Triggers Conversion Cycle 0x0 R/W [3:1] MUX_SEL ADC Input Signal Select 0x0 R/W 0 ADC_EOC ADC End of Conversion Signal 0x0 R 0x04B ADC_OUTPUT [7:0] ADC ADC Output Word 0x0 R 0x04C TX_CURR_MODE [7:4] RESERVED Reserved 0x0 R [3:0] TX_CURR_MODE Read Back Current Transmit Mode 0x0 R 0x04D TX_CURR_STATE 7 RESERVED Reserved 0x0 R [6:0] TX_CURR_STATE Read Back Current Transmit Sequencer Count 0x0 R 0x04E MULT_STATUS [7:4] MULT_CURR_STATE Read Back Current Multiplier Sequencer Count 0x0 R [3:0] MULT_CURR_MODE Read Back Current Multiplier Mode 0x0 R 0x04F REV_ID [7:0] REV_ID Chip Revision ID 0x0 R |
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