ADAR2001ACCZ datasheet(13/39 Pages) AD

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Data Sheet

ADAR2001

Rev. 0 | Page 13 of 39

THEORY OF OPERATION

OVERVIEW

The main elements of the ADAR2001 are an RF input buffer, a

4× frequency multiplier with integrated switchable harmonic

filter, a 1:4 signal splitter, and four differential output PAs that

can drive dipole or similar antennas with differential inputs.

Apply a CW RF input signal between 2.5 GHz and 10 GHz with

a power level of approximately −20 dBm to the RFIN port

(Pin 4), which results in a nominal PA output power of 5 dBm

on each of the differential PA outputs, RFOUTx± (Pin 18,

Pin 19, Pin 23, Pin 24, Pin 28, Pin 29, Pin 33, and Pin 34).

The operation of these subcircuits can be controlled from the

SPI port as well as two programmable state machines, one

focused on multiplier/filter control and the other focused on

transmit control.

RF output power on each channel can be monitored using

individual, on-chip RF detectors. Temperature can also be

observed with a temperature diode. These sensors feed into a

5:1 multiplexer that passes the desired signal to an on-chip,

8-bit ADC.

The ADAR2001 also includes an Analog Devices SPI port that

is used for device configuration and readback. Although the

state machines provide the fastest switching between states, all

functions can also be controlled directly through the SPI port.

INPUT BUFFER, 4× MULTIPLIER, AND BAND-PASS

FILTER

The RF input buffer provides approximately 17 dB of gain and

provides an optimal driver for the 4× multiplier bands. The bias

levels of the input and output stages of the buffer are independently

adjustable through the SPI via Register 0x013. See the Bias Points

section for more information.

The broadband frequency multiplier consists of three parallel

subcircuits. Each subcircuit (low band, mid band, high band) is

optimized to multiply and filter a segment of the total frequency

range (2.5 GHz to 10 GHz input, 10 GHz to 40 GHz output).

Recommended ranges and register settings for each band are

shown in Table 7. Switches at the input and output of the

multiplier block are used to select the subcircuit for the desired

frequency of operation.

Each subcircuit consists of a 4× multiplier and a band-pass

filter (BPF) with an adjustable corner frequency. The bias levels

of the 4× multipliers are adjustable through the SPI using

for more information.

When the input frequency is in the low end of the band of the

subcircuit, the BPF corner frequency must be set to its low

state. Set the associated bit high to set the BPF corner frequency

to its low state. See Table 7.

To complete a full 10 GHz to 40 GHz frequency sweep, the

multiplier/filter block settings must be adjusted seven times to

ensure optimum harmonic rejection and output power. These

seven settings are shown in Table 7. By using the appropriate

subcircuit and filter settings, harmonic distortion across the

10 GHz to 40 GHz range can be kept below −25 dBc. Within

the 20 GHz to 40 GHz range, −30 dBc of harmonic rejection

can be achieved.

In addition to having sleep and active modes, the 4× multipliers

can be set to ready mode. Ready mode is a hybrid state between

sleep and active mode, which does not pass a signal, but allows

fast turn on. Current consumption in ready mode is higher

than sleep mode but lower than in active mode. The switching

time between ready mode and active mode is significantly faster

than from sleep mode to active mode.

DIGITAL STEP ATTENUATOR

Although there is a digital step attenuator inside the multiplier/

filter block of the ADAR2001, it is not intended to be used as a

level control for the output power of the ADAR2001. This

attenuator is meant for reducing the level of harmonic content

coming out of the multipliers before entering the splitter network.

Suggested values for the digital step attenuator vs. RF frequency

are shown in Table 7 and represent a balance between harmonic

performance and output power level. Therefore, altering these

values is not recommended. Note that a value of 0x00 for

ATTN_x (which refers to the ATTN_MDx and ATTN_SPI

bits) corresponds to maximum attenuation.

LOW-PASS/NOTCH FILTER

A low-pass/notch filter is included after the PA outputs to help

reduce any undesired harmonic content before transmission of

the desired signal. RF output frequencies less than 16 GHz

benefit from having this filter enabled. RF output frequencies

more than 16 GHz must have this filter switched out to reduce

any insertion loss due to the filter. Set the associated bit high to

enable the filter. See Table 7.

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