ADAR2001ACCZ datasheet(14/39 Pages) AD

14 / 39 page

ADAR2001

Data Sheet

Rev. 0 | Page 14 of 39

Table 7. Multiplier/Filter Settings for Optimal Harmonic Rejection

Input

Frequency

(GHz)

Output

Frequency

(GHz)

Multiplier Band

BPF

ATTN_x1

Low-Pass/

Notch Filter

MULT_EN_x

MULT_PASS_x

2.50 to 3.00

10 to 12

Low band active (mid and

high bands ready)

Low

0x13

0x7A

0xD3

3.00 to 3.50

12 to 14

Low band active (mid and

high bands ready)

High

0x07

0x7A

0x47

3.50 to 4.00

14 to 16

Low band active (mid and

high bands ready)

High

0x13

0x7A

0x53

4.00 to 5.00

16 to 20

Mid band active (low and

high bands ready)

Low

0x1F

Off

0x6E

0x9F

5.00 to 6.25

20 to 25

Mid band active (low and

high bands ready)

High

0x1F

Off

0x6E

0x1F

6.25 to 8.00

25 to 32

High band active (low and

mid bands ready)

Low

0x1F

Off

0x6B

0x9F

8.00 to 10.00

32 to 40

High band active (low and

mid bands ready)

High

0x1F

Off

0x6B

0x1F

1 ATTN_x refers to the ATTN_MDx and ATTN_SPI bit fields.

2 MULT_EN_x refers to the MULT_EN_MODE_x and MULT_EN_SPI registers.

3 MULT_PASS_x refers to the MULT_PASS_MODE_x and MULT_PASS_SPI registers.

1:4 SIGNAL SPLITTER NETWORK

The output of the multiplier/filter block is then applied to a

1:4 active power splitting network that is composed of two

stages. The first stage is a 1:2 active splitter, which then feeds

the second stage, two 1:2 active splitters. Each output path from

the second stage drives a single PA, which results in a single

input signal being split into four independently controlled

output channels. The bias levels of each splitter stage are

adjustable through the SPI via Register 0x014. See the Bias

Points section for more information.

OUTPUT POWER AMPLIFIERS

There are four PAs, each with an ac-coupled, differential output

operating from 10 GHz to 40 GHz. The differential output is

intended to facilitate direct connection to an antenna with

differential inputs. In applications where a single-ended output

is required, the unused output can be terminated to ground

using a 50 Ω resistor. Terminating the unused output results in

3 dB lower output power (that is, a single-ended output power

of 2 dBm, nominal) along with some degradation in harmonic

rejection. The bias level of the PAs is adjustable through the

SPI. One setting, PA_BIAS in Register 0x015, controls all four

PA bias points. See the Bias Points section for more information.

In normal operation, only one of the four PAs is active at a

time, but the programmability allows all four (or any

combination thereof) to be turned on simultaneously.

Like the 4× multipliers, each PA has three modes of operation:

sleep, ready, and active. Ready mode is a hybrid state between

sleep and active, which does not pass a signal, but allows fast turn

on. Current consumption in ready mode is higher than sleep

mode but lower than active mode. The switching time between

ready mode and active mode is significantly faster than from

sleep mode to active mode.

For the fastest switching times, use of the ready mode is critical.

For example, while Power Amplifier 1 (PA1) is transmitting,

Power Amplifier 2 (PA2) can be set to ready mode. The

transmitter state machine can then be used to put PA1 to sleep

and switch PA2 from ready to active.

POWER DETECTORS AND TEMPERATURE SENSOR

Each transmit channel on the ADAR2001 has a dedicated

power detector with an enable bit in Register 0x049. All the

detectors feed into a 5:1 multiplexer along with the local

temperature sensor. This multiplexer allows the 8-bit on-chip

ADC the flexibility to measure the current output power level

of any channel, or the temperature of the chip itself. To

calculate the approximate temperature in Celsius from the

ADC output code, use the following equation:

TA = (1.31 × ADC_OUTPUT) – 118

where ADC_OUTPUT is the ADC output word in Register 0x04B.

ADC INPUT MULTIPLEXER

The multiplexer position can be programmed using the

MUX_SEL bits (Register 0x04A, Bits[3:1]). The multiplexer has

five valid states, from 0 to 4. Figure 27 shows the multiplexer

mapping.

TO ADC

TEMPERATURE SENSOR

CHANNEL 1 DETECTOR

CHANNEL 2 DETECTOR

CHANNEL 3 DETECTOR

CHANNEL 4 DETECTOR

OUT

Figure 27. ADC Input Multiplexer Mapping

ADAR2001ACCZ 数据表(PDF) 14 Page - Analog Devices

ADAR2001ACCZ 数据表(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

数据表下载

链接网址

ADAR2001ACCZ 数据表(PDF) 14 Page - Analog Devices

ADAR2001ACCZ 数据表(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

数据表 下载

链接网址

数据表下载