Data Sheet

ADAR2001

Rev. 0 | Page 5 of 39

TIMING SPECIFICATIONS

Table 2. SPI Timing

Parameter

Description

Test Conditions/Comments

Min

Typ

Max

Unit

Maximum clock rate

Write only

40

MHz

Write and read

15

MHz

Minimum pulse width high

10

ns

Minimum pulse width low

10

ns

Setup time, SDIO to SCLK

5

ns

Hold time, SDIO to SCLK

5

ns

Data valid, SDO to SCLK

5

ns

Setup time, CS to SCLK

10

ns

SDIO, SDO rise time

Outputs loaded with 10 pF, 10% to 90%

40

ns

SDIO, SDO fall time

Outputs loaded with 10 pF, 10% to 90%

40

ns

Timing Diagrams

CS

DON'T CARE

DON'T CARE

SCLK

DON'T CARE

R/W

A14

A13

A2

A1

A0

D7

D6

D5

D2

D1

D0

DON'T CARE

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

Figure 2. SPI Transaction Structure (MSB First)

CS

DON'T CARE

DON'T CARE

SCLK

DON'T CARE

WRITE

A14

A13

A2

A1

A0

D7

D6

D5

D2

D1

D0

DON'T CARE

SDIO

Figure 3. SPI Write Timing Diagram

CS

DON'T CARE

DON'T CARE

SCLK

DON'T CARE

READ

A14

A13

A2

A1

A0

DON'T CARE

SDIO

D7

D6

D5

D1

D0

SDO

DON'T

CARE

DON'T

CARE

DON'T

CARE

DON'T

CARE

DON'T

CARE

Figure 4. SPI 4-Wire Read Timing Diagram

SPI Block Write Mode

Data can be written to the SPI registers using the block write mode where the register address automatically increments and data for

consecutive registers can be written without sending new address bits. Data writing can be continued indefinitely until CS is raised,

ending the transaction. See Figure 5.

CS

DON'T CARE

DON'T CARE

SCLK

DON'T CARE

WRITE

A14

A13

A1

A0

D7

D6

D1

D0

D7

D6

D1

D0

DON'T CARE

SDIO

FIRST REGISTER ADDRESS

FIRST REGISTER DATA

(n + FIRST REGISTER) DATA

Figure 5. SPI Block Write