ADAR2001ACCZ datasheet(7/39 Pages) AD

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Data Sheet

ADAR2001

Rev. 0 | Page 7 of 39

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VPOS1

GND1

GND2

RFIN

GND3

VREG

VPOS2

TxADV

TxRST

MADV

VPOS3

GND7

RFOUT3+

RFOUT3–

GND8

GND9

GND10

RFOUT2–

RFOUT2+

GND

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND PLANE WITH

LOW THERMAL AND ELECTRICAL IMPEDANCE.

ADAR2001

TOP VIEW

(Not to Scale)

Figure 6. Pin Configuration (Top View, Not to Scale)

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 21, 31, 40

VPOS1, VPOS3, VPOS4, VPOS5

2.5 V Power Supply for the Analog Section. Connect decoupling capacitors (one 10 nF and

one 100 pF on each pin, and a 1 μF for the rail) to the ground plane as close as possible to

these pins.

2, 3, 5, 16, 17, 20, 22,

25 to 27, 30, 32,

35 to 39

GND1 to GND17

Ground. Connect all ground pins to a ground plane with low thermal and electrical

impedance.

RFIN

RF Input. RFIN is a single-ended, 50 Ω input operating from 2.5 GHz to 10 GHz, ac-coupled

internally. The nominal input power level is −20 dBm.

VREG

1.8 V Low Dropout (LDO) Regulator Output. Directly connect VREG to Pin 7 (VPOS2).

VPOS2

1.8 V Power Supply for the Digital Section. Directly connect this supply to Pin 6 (VREG).

Place a 1 μF capacitor to ground as close as possible to VPOS2.

TxADV

Transmitter State Machine Advance. If the state machine is enabled, pulsing TxADV

advances the transmitter state machine to the next state in its cycle. If currently at the end

of the cycle, pulsing TxADV returns the pointer to the mode defined in TX_STATE_1

(Register 0x019, Bits[7:4]).

TxRST

Transmitter State Machine Reset. If the state machine is enabled, TxRST immediately sets

the transmit control state machine back to the configuration in the TX_EN1_MODE_0 and

TX_EN2_MODE_0 registers (Register 0x050 and Register 0x051).

MADV

Multiplier/Filter State Machine Advance. If the state machine is enabled, pulsing MADV

advances the multiplier/filter state machine to the next state in its cycle. If currently at the

end of the cycle, pulsing MADV returns the pointer to the mode defined in MULT_STATE_1

(Register 0x03C, Bits[7:4]).

MRST

Multiplier/Filter State Machine Reset. If the state machine is enabled, MRST immediately

sets the multiplier/filter state machine back to the configuration defined in the

MULT_EN_MODE_0 and MULT_PASS_MODE_0 registers (Register 0x070 and Register 0x071).

SCLK

Serial Clock. The SCLK pin is used to clock data into and out of the SPI interface.

SDIO

Serial Data Input/Output. The SDIO pin is a high impedance data input for clocking in

information. SDIO can also be used to read out data if Register 0x000, Bits[4:3] are set low

(default).

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