ADAR2001ACCZ datasheet(21/39 Pages) AD

21 / 39 page

Data Sheet

ADAR2001

Rev. 0 | Page 21 of 39

For example, when the ADAR2001 is configured for a frequency

sweep (as shown in Figure 29), if the TX_SLP_CTRL bit

(Register 0x016, Bit 6) is set, when the multiplier/filter sequencer

is reset, the transmitter state machine is forced to sleep as well.

This means that the transmitter state machine does not need to

have a state dedicated to sleep if it only needs to sleep when the

multiplier/ filter sleeps. Furthermore, because the multiplier/

filter sleep state is controlling the sleep state of the transmitter,

bringing the multiplier/filter out of sleep also brings the

transmitter out of sleep, all of which is controlled with either

the SPI or one external line (MADV).

SEQUENCER SLEEP HOLD

By default, when one of the sequencers is forced asleep using one

of the sleep control bits (MULT_SLP_CTRL or TX_SLP_CTRL),

the counter for the sequencer being controlled can still be

advanced. Because of this behavior, it is possible for a state

machine to be put to sleep in one condition and brought out of

sleep in another, depending on whether the sequencer advance or

reset signals were exercised while the sequencer was sleeping.

If this behavior is undesired, the sleep hold bits (MULT_SLP_

HOLD and TX_SLP_HOLD) can be asserted to force the

associated state machine counter to ignore any inputs on the

sequencer advance line. The counter also ignores advance

signals coming from the SPI.

Note that the state machine counters always respond to a reset

signal, even when the sleep hold bit is high.

When sleep hold is used, care must be taken when bringing the

state machines out of sleep mode to ensure that the desired

modes are reached. If the advance pins for both sequencers are

pulsed too closely together under this condition, it is possible

for the sequencer being controlled to not move into the expected

state. To prevent this, the advance pulses must be staggered

such that the rising edges are separated by a minimum of 3 ns

with the pulse of the controlled sequencer coming second. See

Figure 32 for an example of how to pulse the sequencers under

this condition.

TX_SLP_HOLD REGISTER 0x016, BIT 5 = 1

TX_SLP_CTRL REGISTER 0x016, BIT 6 = 1

MULT_SLP_HOLD REGISTER 0x018, BIT 5 = 0

MULT_SLP_CTRL REGISTER 0x018, BIT 6 = 0

MADV

TxADV

≥3ns

Figure 32. Example of How to Pulse the Sequencer Advance Pins to Ensure

Advancement with Transmitter State Machine Sleep Hold Enabled

SEQUENCER CONTROL LATCH BYPASS

Typically, when a sequencer control line is pulsed, the

upcoming state is loaded on the rising edge of the control pulse

and latched to the various signal blocks on the falling edge of

the same pulse. The latching helps to line up all the internal

control signals so that the changes take place simultaneously.

It is possible to bypass the latching of the internal control

signals by setting the bypass bits (TX_CTL_LATCH_BYP and

MULT_CTL_LATCH_BYP) in the sequencer setup registers

(Register 0x016, Bit 4 and Register 0x018, Bit 4).

Bypassing the latch results in the new state taking effect as soon

as possible after the rising edge. Because the internal control

signals are not aligned, the overall switching time between

states can increase when compared to using the latch. Also,

glitches are more likely to occur in the internal control signals,

resulting in undesired transients in the RF blocks.

Note that this latch is the last check before any new data is sent

to the various individual blocks. Therefore, when using the

ADAR2001 in manual or SPI mode (sequencers disabled), the

latching must be bypassed. If latching is not bypassed, the

blocks never receive the new instructions unless the external

sequencer pins are pulsed. However, this issue is uncommon

because the sequencers are disabled in this mode of operation.

PARALLEL CHIP CONTROL

Up to 16 devices (a total of 64 channels) can be driven by a

single set of four state machine control lines, three common SPI

lines, and a CS line for each chip. Using this method, the total

number of digital control lines is 7 + N, where N is the number

of ADAR2001 ICs (see Figure 33 for a basic diagram). Parallel

chip control can be used to minimize the total number of digital

control lines. The SPI lines can be reduced to two common

lines if 3-wire mode is selected by setting the SDOACTIVE and

SDOACTIVE_ bits (Register 0x00, Bit 4 and Bit 3, respectively)

to low. If 3-wire SPI mode is used, the total number of digital

lines to 6 + N.

ADAR2001

(1)

COMMON

SEQUENCER

LINES

SEQUENCERS

SPI

SPI CS

LINES

COMMON

SPI

LINES

SEQUENCERS

ADAR2001

(2)

ADAR2001

(16)

Figure 33. SPI and State Machine Digital Lines for Addressing and

Controlling Up to 16 ADAR2001 Devices in Parallel

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