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ADGM1004

Data Sheet

Rev. D | Page 22 of 32

THEORY OF OPERATION

The ADGM1004 is a wideband SP4T switch fabricated using

Analog Devices MEMS switch technology. This technology

enables high power, low loss, low distortion GHz switches for

use in demanding RF applications.

The MEMS switch simultaneously brings together high

frequency RF performance and 0 Hz/dc precision performance.

This combination, coupled with superior reliability and a tiny

surface-mountable form factor, makes the MEMS switch an

ideal switching solution for all RF and precision signal

instrumentation needs.

Figure 44 shows a cross section of the switch with dimensions.

The switch is an electrostatically actuated cantilever beam

connected in a 3-terminal configuration. Functionally, the switch is

analogous to a field effect transistor (FET). The terminals can

be used as a source, gate, or drain.

SILICON

SILICON CAP

SOURCE

DRAIN

CANTILEVER BEAM

GATE

CONTACT GAP

METAL

Figure 44. Cross Section of the MEMS Switch Design Showing the Cantilever

Switch Beam (Not to Scale)

When a dc actuation voltage is applied between the gate

electrode and the source (the switch beam), an electrostatic

force is generated, resulting in attracting the beam toward the

substrate. A separate on-board driver IC generates the 80 V bias

voltage used for actuation.

When the bias voltage between the gate and the source exceeds

the threshold voltage of the switch (VTH) the contacts on the

beam touch the drain, which completes the circuit between the

source and the drain and turns the switch on. When the bias

voltage is removed, that is, the 0 V on the gate electrode, the

beam acts as a spring generating a sufficient restoring force to

open the connection between the source and the drain, thus

breaking the circuit and turning the switch off.

The silicon cap covering the switch die is shown in Figure 44. This

cap hermetically seals the switch, which improves reliability.

The switch contacts do not suffer from dry switching or low power

switching lifetime degradation.

PARALLEL DIGITAL INTERFACE

The ADGM1004 is controlled via a parallel digital interface.

Standard complimentary metal-oxide semiconductor (CMOS)/

low voltage transistor to transistor logic (LVTTL) signals

applied through this interface control the actuation or release of

all ADGM1004 switch channels. Gate signals applied are

boosted to provide the required voltages required to actuate the

MEMS switch.

Setting the PIN/SPI pin low enables the parallel digital interface

in 4-wire SP4T mode. In parallel mode, Pin 1 to Pin 4 (IN1 to

IN4) control the switching functions of the ADGM1004. When

a Logic 1 is applied to one of these pins, the gate of the

corresponding switch is activated and the switch turns on.

Conversely, when a Logic 0 is applied to one of these pins, the

switch turns off. Note that it is possible to connect more than

one RFx input to RFC at a time. See Table 6 for the ADGM1004

truth table.

Table 6. Truth Table When in Parallel Digital Interface Mode

IN1

IN2

IN3

IN4

RF1 to RFC

RF2 to RFC

RF3 to RFC

RF4 to RFC

Off

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