ADGM1004JCPZ-R2 datasheet(23/32 Pages) AD

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Data Sheet

ADGM1004

Rev. D | Page 23 of 32

SPI DIGITAL INTERFACE

The ADGM1004 can be controlled via a digital SPI when the

PIN/SPI pin is high. The SPI is compatible with SPI Mode 0

(clock polarity (CPOL) = 0, clock phase (CPHA) = 0) and Mode 3

(CPOL = 1, CPHA = 1) and it operates with SCLK frequencies up

to 10 MHz. When the SPI is active, the default mode is

addressable, in which, the device registers are accessed by a 16-bit

SPI command that is bound by the state of the CS pin. The

ADGM1004 can also operate in daisy-chain mode.

The SPI interface pins of the ADGM1004 are CS, SCLK, SDI,

and SDO. Hold the CS pin low when using the SPI. The data on

the SDI pin is captured on the rising edge of SCLK, and data is

propagated out on the SDO pin on the falling edge of SCLK. The

SDO pin has a push pull output driver architecture. Therefore,

the ADGM1004 does not require pull-up resistors. The two

modes of SPI operation are: addressable and daisy-chain.

Addressable Mode

Addressable mode is the default mode for the ADGM1004

upon power-up. A single SPI frame in addressable mode is bound

by a CS falling edge and the succeeding CS rising edge. The

frame is comprised of 16 SCLK cycles. The timing diagram for

addressable mode is shown in Figure 45. The first SDI signal bit

indicates if the SPI command is a read or write command. The

next seven bits determine the target register address. The

remaining eight bits provide the data to the addressed register.

The first eight bits are ignored during a read command because

the SDO pin propagates out the data contained in the addressed

The target register address of an SPI command is determined on

the eighth SCLK rising edge. Data from this register propagates

out on the SDO pin from the 9th to the 16th SCLK falling edge

during SPI reads. A register write occurs on the 16th SCLK rising

edge during SPI writes. During any SPI command, the SDO pin

sends out eight alignment bits on the first eight SCLK falling

edges. The alignment bits observed at the SDO pin are 0x25.

SDO

R/W

567

SDI

SCLK

Figure 45. Addressable Mode Timing Diagram

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