ST7LITE3 datasheet(58/167 Pages) STMICROELECTRONICS

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ST7LITE3

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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

Dead Time Generation

A dead time can be inserted between PWM0 and

PWM1 using the DTGR register. This is required

for half-bridge driving where PWM signals must

not be overlapped. The non-overlapping PWM0/

PWM1 signals are generated through a program-

mable dead time by setting the DTE bit.

Dead time value = DT[6:0] x Tcounter1

DTGR[7:0] is buffered inside so as to avoid de-

forming the current PWM cycle. The DTGR effect

will take place only after an overflow.

Notes:

1. Dead time is generated only when DTE=1 and

DT[6:0]

≠ 0. If DTE is set and DT[6:0]=0, PWM out-

put signals will be at their reset state.

2. Half Bridge driving is possible only if polarities of

PWM0 and PWM1 are not inverted, i.e. if OP0 and

OP1 are not set. If polarity is inverted, overlapping

PWM0/PWM1 signals will be generated.

Figure 38. Dead Time Generation

In the above example, when the DTE bit is set:

– PWM goes low at DCR0 match and goes high at

ATR1+Tdt

– PWM1 goes high at DCR0+Tdt and goes low at

ATR match.

With this programmable delay (Tdt), the PWM0

and PWM1 signals which are generated are not

overlapped.

DCR0+1

ATR1

DCR0

Tdt

Tdt = DT[6:0] x Tcounter1

PWM 0

PWM 1

CNTR1

CK_CNTR1

Tcounter1

OVF

PWM 0

PWM 1

counter = DCR0

counter = DCR1

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