ST7LITE3 datasheet(68/167 Pages) STMICROELECTRONICS

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ST7LITE3

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DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)

Bit 4 = OVFIE2 Overflow interrupt 2 enable

This bit is read/write by software and controls the

overflow interrupt of counter2.

0: Overflow interrupt disabled.

1: Overflow interrupt enabled.

Bit 3 = OVF2 Overflow Flag.

This bit is set by hardware and cleared by software

by reading the ATCSR2 register. It indicates the

transition of the counter2 from FFFh to ATR2 val-

ue.

0: No counter overflow occurred

1: Counter overflow occurred

Bit 2 = ENCNTR2 Enable counter2

This bit is read/write be software and switches the

second counter CNTR2. If this bit is set, PWM2

and PWM3 will be generated using CNTR2.

0: CNTR2 stopped.

1: CNTR2 starts running.

Bit 1= TRAN2 Transfer enable2

This bit is read/write by software, cleared by hard-

ware after each completed transfer and set by

hardware after reset. It controls the transfers on

CNTR2.

It allows the value of the Preload DCRx registers

to be transferred to the Active DCRx registers after

the next overflow event.

The OPx bits are transferred to the shadow OPx

bits in the same way.

(Only DCR2/DCR3 can be controlled with this bit)

Bit 0 = TRAN1 Transfer enable 1

This bit is read/write by software, cleared by hard-

ware after each completed transfer and set by

hardware after reset. It controls the transfers on

CNTR1. It allows the value of the Preload DCRx

registers to be transferred to the Active DCRx reg-

isters after the next overflow event.

The OPx bits are transferred to the shadow OPx

bits in the same way.

AUTORELOAD REGISTER2 (ATR2H)

Read / Write

Reset Value: 0000 0000 (00h)

AUTORELOAD REGISTER (ATR2L)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 11:0 = ATR2[11:0] Autoreload Register 2.

This is a 12-bit register which is written by soft-

ware. The ATR2 register value is automatically

loaded into the upcounter CNTR2 when an over-

flow of CNTR2 occurs. The register value is used

set

the

PWM2/PWM3

frequency

when

ENCNTR2 is set.

DEAD TIME GENERATOR REGISTER (DTGR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7 = DTE Dead Time Enable

This bit is read/write by software. It enables a dead

time generation on PWM0/PWM1.

0: No Dead time insertion.

1: Dead time insertion enabled.

Bit 6:0 = DT[6:0] Dead Time Value

These bits are read/write by software. They define

the dead time inserted between PWM0/PWM1.

Dead time is calculated as follows:

Dead Time = DT[6:0] x Tcounter1

ATR11 ATR10

ATR9

ATR8

ATR7

ATR6

ATR5

ATR4

ATR3

ATR2

ATR1

ATR0

DTE

DT6

DT5

DT4

DT3

DT2

DT1

DT0

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