ST7LITE3 datasheet(113/167 Pages) STMICROELECTRONICS

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ST7LITE3

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LINSCI

™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d)

11.5.10 LIN Mode Register Description

STATUS REGISTER (SCISR)

Read Only

Reset Value: 1100 0000 (C0h)

Bits 7:4 = Same function as in SCI mode, please

refer to Section 11.5.8 SCI Mode Register De-

scription.

Bit 3 = LHE LIN Header Error.

During LIN Header this bit signals three error

types:

– The LIN Synch Field is corrupted and the SCI is

blocked in LIN Synch State (LSF bit=1).

– A timeout occurred during LIN Header reception

– An overrun error was detected on one of the

header field (see OR bit description in Section

11.5.8 SCI Mode Register Description)).

An interrupt is generated if RIE=1 in the SCICR2

bit must first be reset (to exit LIN Synch Field state

and then to be able to clear LHE flag). Then it is

cleared by the following software sequence : an

access to the SCISR register followed by a read to

the SCIDR register.

0: No LIN Header error

1: LIN Header error detected

Note:

Apart from the LIN Header this bit signals an Over-

run Error as in SCI mode, (see description in Sec-

tion 11.5.8 SCI Mode Register Description)

Bit 2 = NF Noise flag

In LIN Master mode (LINE bit = 1 and LSLV bit = 0)

this bit has the same function as in SCI mode,

please refer to Section 11.5.8 SCI Mode Register

Description

In LIN Slave mode (LINE bit = 1 and LSLV bit = 1)

this bit has no meaning.

Bit 1 = Bit 1 = FE Framing error.

In LIN slave mode, this bit is set only when a real

framing error is detected (if the stop bit is dominant

(0) and at least one of the other bits is recessive

(1). It is not set when a break occurs, the LHDF bit

is used instead as a break flag (if the LHDM bit=0).

It is cleared by a software sequence (an access to

the SCISR register followed by a read to the

SCIDR register).

0: No Framing error

1: Framing error detected

Bit 0 = PE Parity error.

This bit is set by hardware when a LIN parity error

occurs (if the PCE bit is set) in receiver mode. It is

cleared by a software sequence (a read to the sta-

tus register followed by an access to the SCIDR

data register). An interrupt is generated if PIE=1 in

the SCICR1 register.

0: No LIN parity error

1: LIN Parity error detected

CONTROL REGISTER 1 (SCICR1)

Read/Write

Reset Value: x000 0000 (x0h)

Bits 7:3 = Same function as in SCI mode, please

refer to Section 11.5.8 SCI Mode Register De-

scription.

Bit 2 = PCE Parity control enable.

This bit is set and cleared by software. It selects

the hardware parity control for LIN identifier parity

check.

0: Parity control disabled

1: Parity control enabled

When a parity error occurs, the PE bit in the

SCISR register is set.

Bit 1 = Reserved

Bit 0 = Same function as in SCI mode, please refer

to Section 11.5.8 SCI Mode Register Description.

TDRE

RDRF

IDLE

LHE

SCID

WAKE

PCE

PIE

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