AD4020/AD4021/AD4022

Data Sheet

Rev. B | Page 26 of 39

Serial Clock Frequency Requirements

The AD4020/AD4021/AD4022 digital interface minimizes the

SCK frequency required for reading back conversion results, even

when operating at a high throughput. The minimum SCK frequen-

cy required for a given application depends on the number of bits

being read on SDO, whether turbo mode is enabled or disabled,

and the throughput in use. See Table 13 for several examples of

SCK frequency requirements for different throughputs.

conversion result plus status bits when turbo mode is enabled is

calculated with the following equation:

DS

SCK

CYC

QUIET1

EN

QUIET2

NN

f

t

t

tt

+

>

−

−−

where:

described in Table 2.

The minimum SCK frequency required to access the conversion

result plus status bits when turbo mode is not enabled is

calculated with the following equation:

DS

SCK

CYC

CONV

EN

QUIET2

NN

f

t

t

tt

+

>

−

−−

described in Table 2.

Table 12. Configuration Register

Bits

Bit Name

Description

Reset

[7:5]

Reserved

Reserved memory.

0x0

R

4

Status bits enable

Enables status bits (see the Status Bits section).

0x0

R/W

0: disables status bits.

1: enables status bits.

3

Span compression enable

Enables span compression (see the Input Span Compression section).

0x0

R/W

0: disables span compression.

1: enables span compression.

2

High-Z mode enable

Enables high-Z mode (see the High-Z Mode section).

0x0

R/W

0: disables high-Z mode.

1: enables high-Z mode.

1

Turbo mode enable

Enables turbo mode.

0x0

R/W

0: disables turbo mode.

1: enables turbo mode.

0

OV clamp flag

Indicates an overvoltage event triggered the input overvoltage clamp circuit (see

the Input Overvoltage Clamp Circuit section). This bit is sticky, and clears only

when read after the overvoltage event has ended.

0x1

R

0: indicates an overvoltage event has occurred.

1: indicates no overvoltage event has occurred.

1

R is read-only and R/W is read/write. Read only bits cannot be updated with a register write operation. R/W bits can be updated with a register write operation.

Table 13. SCK Frequency Requirements for Various Throughputs

CS Mode

Throughput

Minimum SCK Frequency (MHz)

3-Wire and 4-Wire Turbo Modes

1.8 MSPS (AD4020)

71

1 MSPS (AD4020, AD4021)

28

500 kSPS (AD4020, AD4021, AD4022)

12

100 kSPS (AD4020, AD4021, AD4022)

2.5

3-Wire and 4-Wire Turbo Modes with Six Status Bits

1.8 MSPS (AD4020)

92

1 MSPS (AD4020, AD4021)

36

500 kSPS (AD4020, AD4021, AD4020)

16

100 kSPS (AD4020, AD4021, AD4022)

3

3-Wire and 4-Wire Modes

1.6 MSPS (AD4020)

98

1 MSPS (AD4020, AD4021)

35

500 kSPS (AD4020, AD4021, AD4022)

13

100 kSPS (AD4020, AD4021, AD4022)

2.5

3-Wire and 4-Wire Modes with Status Word

1.4 MSPS (AD4020)

90

1 MSPS (AD4020, AD4021)

45

500 kSPS (AD4020, AD4021, AD4022)

17

100 kSPS (AD4020, AD4021, AD4022)

3