Data Sheet

AD4020/AD4021/AD4022

Rev. B | Page 23 of 39

REF

VDD

VIO

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD4020/

AD4021/

AD4022

1.8V TO 5V

+IN

–IN

R4

1kΩ

DIFFERENTIAL

AMPLIFIER

R1

1kΩ

V–

AMP

0

1.8V

10µF

R3

1k

Ω

V+

–OUT

+OUT

R2

1kΩ

R

R

0.1µF

HOST

SUPPLY

C

C

REF

V+ = +5V

LDO

10kΩ

10kΩ

4.096V

0.1µF

0.1µF

3-WIRE/4-WIRE

INTERFACE

DIGITAL HOST

(MICROPROCESSOR/

FPGA)

Figure 44. Typical Application Diagram for Single-Ended to Differential Conversion with a Fully Differential Amplifier

Single to Differential Driver

The AD4020/AD4021/AD4022 requires a differential input

signal for proper operation. For applications using a single-

ended analog signal, either bipolar or unipolar, a fully differential

amplifier, such as the ADA4940-1 or ADA4945-1, can be used

to convert the single-ended signal to a differential signal, as

shown in Figure 44.

High Frequency Input Signals

The AD4020/AD4021/AD4022 ac performance over a wide

input frequency range is shown in Figure 17 and Figure 20.

Unlike other traditional SAR ADCs, the AD4020/AD4021/

AD4022 maintain exceptional ac performance for input

frequencies up to the Nyquist frequency with minimal

performance degradation. Note that the input frequency is

limited to the Nyquist frequency of the sample rate in use.

Multiplexed Applications

The AD4020/AD4021/AD4022 significantly reduce system

complexity for multiplexed applications that require superior

performance in terms of noise, power, and throughput. Figure 45

shows a simplified block diagram of a multiplexed data

acquisition system including a multiplexer, an ADC driver, and the

precision SAR ADC.

SAR ADC

ADC

DRIVER

MULTIPLEXER

R

R

R

C

C

C

C

Figure 45. Multiplexed Data Acquisition Signal Chain Using the

AD4020/AD4021/AD4022

Switching multiplexer channels typically results in large voltage

steps at the ADC inputs. To ensure an accurate conversion result,

the step must be given adequate time to settle before the ADC

samples the inputs (on the rising edge of CNV). The settling

time error is dependent on the drive circuitry (multiplexer and

ADC driver), RC filter values, and the time when the multiplexer

channels are switched. Switch the multiplexer channels

conversion to maximize settling time and to prevent corruption

of the conversion result. To avoid conversion corruption, do not

current conversion is possibly corrupted.

EASE OF DRIVE FEATURES

Input Span Compression

In single-supply applications, it is recommended to use the full

range of the ADC. However, the amplifier can have some

headroom and footroom requirements, which can be a problem,

even if it is a rail-to-rail input and output amplifier. The AD4020/

AD4021/AD4022 include a span compression feature that

increases the headroom and footroom available to the amplifier

by reducing the input range by 10% from the top and bottom of the

range while still accessing all available ADC codes (see

Figure 46). The SNR decreases by approximately 1.9 dB (20 ×

log(8/10)) for the reduced input range when span compression is

enabled. Span compression is disabled by default but is enabled by

writing to the relevant register bit (see the Digital Interface

section).

ADC

DIGITAL OUTPUT

CODES

+FSR

–FSR

ANALOG

INPUT

5V

IN+

Figure 46. Span Compression