AD4020BCPZ-R2 datasheet(24/39 Pages) AD

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AD4020/AD4021/AD4022

Data Sheet

Rev. B | Page 24 of 39

High-Z Mode

The AD4020/AD4021/AD4022 incorporate high-Z mode, which

reduces the nonlinear charge kickback when the capacitor DAC

switches back to the input at the start of acquisition. Figure 28

shows the analog input current of the AD4020/AD4021/AD4022

with high-Z mode enabled and disabled. The low input current

makes the ADC easier to drive than the traditional SAR ADCs

available in the market, even with high-Z mode disabled. The

input current reduces further to submicroampere range when

high-Z mode is enabled. The high-Z mode is disabled by default,

but can be enabled by writing to the configuration register (see

Table 12). Disable high-Z mode for input frequencies above

100 kHz or when multiplexing.

To achieve the optimum data sheet performance from traditional

high resolution precision SAR ADCs, system designers must often

use a dedicated high power, high speed amplifier to drive the

switched capacitor SAR ADC inputs. High-Z mode allows a

choice of lower power and lower bandwidth precision amplifiers

with a lower RC filter cutoff to drive the ADC, removing the need

for dedicated high speed ADC drivers, which saves system power,

size, and cost in precision, low bandwidth applications. High-Z

mode allows the amplifier and RC filter in front of the ADC to

be chosen based on the signal bandwidth of interest, and not

based on the settling requirements of the switched capacitor SAR

ADC inputs. High-Z mode also improves THD performance and

reduces analog input current for input signals up to 100 kHz.

Additionally, the AD4020/AD4021/AD4022 can be driven with

a much higher source impedance than traditional SARs, which

means the resistor in the RC filter can have a value 10 times

larger than previous SAR designs and, with high-Z mode enabled,

can tolerate even greater impedance. Figure 26 shows the THD

performance for various source impedances with high-Z mode

disabled and enabled.

Figure 47 and Figure 48 show the AD4020/AD4021/AD4022 SNR

and THD performance using the ADA4077-1 (supply current

per amplifier (ISY) = 400 μA) and ADA4610-1 (ISY = 1.50 mA)

precision amplifiers when driving the AD4020/AD4021/AD4022

at full throughput for high-Z mode both enabled and disabled

with various RC filter values. These amplifiers achieve +96 dB

to +99 dB typical SNR and close to −110 dB typical THD with

high-Z enabled for a 2.27 MHz RC bandwidth. THD is

approximately 10 dB better with high-Z mode enabled, even for

large R values greater than 200 Ω. SNR maintains close to

99 dB, even with a low RC filter cutoff.

100

260kHz

1.3kΩ

470pF

498kHz

680Ω

470pF

2.27MHz

390Ω

180pF

1.3MHz

680Ω

180pF

4.42MHz

200Ω

180pF

RC FILTER BANDWIDTH (Hz)

RESISTOR (Ω), CAPACITOR (pF)

ADA4077-1 HIGH-Z DISABLED

ADA4077-1 HIGH-Z ENABLED

ADA4610-1 HIGH-Z DISABLED

ADA4610-1 HIGH-Z ENABLED

Figure 47. SNR vs. RC Filter Bandwidth for Various Precision ADC Drivers,

fIN = 1 kHz (See the Typical Performance Characteristics Section for

Operating Conditions)

–80

–84

–92

–100

–88

–96

–104

–112

–108

–116

–120

260kHz

1.3kΩ

470pF

498kHz

680Ω

470pF

2.27MHz

390Ω

180pF

1.3MHz

680Ω

180pF

4.42MHz

200Ω

180pF

RC FILTER BANDWIDTH (Hz)

RESISTOR (Ω), CAPACITOR (pF)

ADA4077-1 HIGH-Z DISABLED

ADA4077-1 HIGH-Z ENABLED

ADA4610-1 HIGH-Z DISABLED

ADA4610-1 HIGH-Z ENABLED

Figure 48. THD vs. RC Filter Bandwidth for Various Precision ADC Drivers,

fIN = 1 kHz (See the Typical Performance Characteristics Section for

Operating Conditions)

When high-Z mode is enabled, the ADC consumes approximately

2.0 mW per MSPS of extra power. However, this additional power

is still significantly lower than using dedicated ADC drivers like the

ADA4807-1. For any system, the front end usually limits the

overall ac/dc performance of the signal chain. The ADA4077-1

and ADA4610-1 data sheets of the selected precision amplifiers (see

Figure 47 and Figure 48) show that their own noise and

distortion performance dominates the SNR and THD

specification at a certain input frequency.

Long Acquisition Phase

The AD4020/AD4021/AD4022 also feature a fast conversion

time of 320 ns, which results in a long acquisition phase. The

acquisition is further extended by a key feature of the AD4020/

AD4021/AD4022. The ADC returns to the acquisition phase

typically 100 ns before the end of the conversion. This feature

provides an even longer time for the ADC to acquire the new

input voltage. A longer acquisition phase reduces the settling

requirement on the driving amplifier, and a lower power and

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