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Data Sheet

AD4020/AD4021/AD4022

Rev. B | Page 37 of 39

LAYOUT GUIDELINES

The PCB that houses the AD4020/AD4021/AD4022 must be

designed so that the analog and digital sections are physically

separated, such as on opposite sides of the device as shown in

Figure 67. The pinout of the AD4020/AD4021/AD4022, with

the analog signals on the left side and the digital signals on the

right side, helps to separate the analog and digital signals.

Avoid running digital lines under the device because they couple

noise onto the die, unless a ground plane under the AD4020/

AD4021/AD4022 is used as a shield. Fast switching signals,

such as CNV or clocks, must not run near analog signal paths.

Avoid crossover of digital and analog signals.

At least one ground plane must be used. The ground plane can

be common or split between the digital and analog sections. In

the latter case, join the planes underneath the

AD4020/AD4021/AD4022 devices.

The AD4020/AD4021/AD4022 voltage reference input (REF)

has a dynamic input impedance. Decouple the REF pin with

minimal parasitic inductances by placing the reference decoupling

ceramic capacitor close to (ideally right up against) the REF and

GND pins, and connect them with wide, low impedance traces.

Finally, decouple the VDD and VIO power supplies of the

AD4020/AD4021/AD4022 with ceramic capacitors, typically

0.1 µF, placed close to the AD4020/AD4021/AD4022 and

connected using short, wide traces to provide low impedance paths

and to reduce the effect of glitches on the power supply lines.

An example of the AD4020 layout following these rules is

shown in Figure 67 and Figure 68. Note that the AD4021/AD4022

layout is equivalent to the AD4020 layout.

EVALUATING THE AD4020/AD4021/AD4022

PERFORMANCE

Other recommended layouts for the AD4020/AD4021/AD4022

are outlined in the user guide of the evaluation board for the

AD4020 (EVAL-AD4020FMCZ). The evaluation board package

includes a fully assembled and tested evaluation board with the

AD4020, the UG-1042 user guide, and software for controlling

the board from a PC via the EVAL-SDP-CH1Z. The EVAL-

AD4020FMCZ can also be used to evaluate the AD4021/AD4022

by limiting the throughput to 1 MSPS and 500 kSPS, respectively,

in the software (see UG-1042 for more information).

Figure

67. Example Layout of the AD4020 (Top Layer)

Figure

68. Example Layout of the AD4020 (Bottom Layer)

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