20-Bit, 1.8 MSPS/1 MSPS/500 kSPS,

Easy Drive, Differential SAR ADCs

Data Sheet

AD4020/AD4021/AD4022

Rev. B

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FEATURES

Easy Drive

Greatly reduced input kickback

Input current reduced to 0.5 μA/MSPS

Enhanced acquisition phase, ≥77% of cycle time at 1 MSPS

First conversion accurate, no latency or pipeline delay

Input span compression for single-supply operation

Fast conversion allows low SPI clock rates

Input overvoltage clamp protection sinks up to 50 mA

SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface

High performance

Throughput: 1.8 MSPS/1 MSPS/500 kSPS options

INL: ±3.1 ppm maximum

Guaranteed 20-bit no missing codes

Oversampled dynamic range

104 dB for OSR = 2

131 dB for OSR = 1024

Low power

Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface

2.7 mW at 500 kSPS (VDD only)

83 μW at 10 kSPS, 15 mW at 1.8 MSPS (total power)

10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP

Pin compatible with AD4003/AD4007/AD4011 family

Guaranteed operation: −40°C to +125°C

APPLICATIONS

Automatic test equipment

Machine automation

Medical equipment

Battery-powered equipment

Precision data acquisition systems

Instrumentation and control systems

FUNCTIONAL BLOCK DIAGRAM

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD4020/AD4021/AD4022

20-BIT

SAR ADC

SERIAL

INTERFACE

VIO

REF

VDD

0

0

HIGH-Z

MODE

CLAMP

SPAN

COMPRESSION

TURBO

MODE

STATUS

BITS

2.5V TO 5V

1.8V

10µF

1.8V TO 5V

3-WIRE OR

4-WIRE SPI

INTERFACE

(DAISY

CHAIN, CS)

Figure 1.

GENERAL DESCRIPTION

The AD4020/AD4021/AD4022 are high accuracy, high speed,

low power, 20-bit, Easy Drive, precision successive approximation

register (SAR) analog-to-digital converters (ADCs) that operate

is applied externally and can be set independent of the supply

voltage. The AD4020/AD4021/AD4022 power scales linearly

with throughput.

Easy Drive features reduce both signal chain complexity and power

consumption while enabling higher channel density. The reduced

input current, particularly in high-Z mode, coupled with a long

signal acquisition phase, eliminates the need for a dedicated

ADC driver. Easy Drive broadens the range of companion circuitry

that is capable of driving these ADCs (see Figure 2).

Input span compression eliminates the need to provide a

negative supply to the ADC driver amplifier while preserving

access to the full ADC code range. The input overvoltage clamp

protects the ADC inputs against overvoltage events, minimizing

disturbances on the reference pin, and eliminating the need for

external protection diodes.

Fast device throughput up to 1.8 MSPS allows users to

accurately capture high frequency signals and to implement

oversampling techniques to alleviate the challenges associated

with antialias filter designs. Decreased serial peripheral interface

(SPI) clock rate requirements reduce digital input/output power

consumption, broadens digital host options, and simplifies the

task of sending data across digital isolation. The SPI-compatible

serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V

logic by using the separate VIO logic supply.

18

–15

–9

–3

6

12

15

–12

–6

0

3

9

–5

–3

–1

5

3

1

INPUT DIFFERENTIAL VOLTAGE (V)

25°C HIGH-Z ENABLED, 1.8MSPS

25°C HIGH-Z DISABLED, 1.8MSPS

Figure 2. Input Current vs. Input Differential Voltage