Data Sheet

AD4020/AD4021/AD4022

Rev. B | Page 7 of 39

TIMING SPECIFICATIONS

otherwise noted. See Figure 49 to Figure 52, Figure 54, Figure 56, Figure 58, Figure 60, Figure 62, Figure 64, and Figure 66 for timing

diagrams.

Table 2. Digital Interface Timing

Symbol

Min

Typ

Max

Unit

CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE

300

320

350

ns

AD4020

325

ns

AD4021

770

ns

AD4022

1770

ns

TIME BETWEEN CONVERSIONS

AD4020

555

ns

AD4021

1000

ns

AD4022

2000

ns

10

ns

SCK PERIOD

VIO > 2.7 V

9.8

ns

VIO > 1.7 V

12.3

ns

VIO > 2.7 V

20

ns

VIO > 1.7 V

25

ns

SCK

Low Time

3

ns

High Time

3

ns

Falling Edge to Data Remains Valid Delay

1.5

ns

Falling Edge to Data Valid Delay

VIO > 2.7 V

7.5

ns

VIO > 1.7 V

10.5

ns

CNV OR SDI LOW TO SDO D17 MSB VALID DELAY (CS MODE)

VIO > 2.7 V

10

ns

VIO > 1.7 V

13

ns

CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY

200

ns

60

ns

CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE)

20

ns

SDI

Valid Setup Time from CNV Rising Edge

2

ns

Valid Hold Time from CNV Rising Edge (CS Mode)

2

ns

Valid Setup Time from SCK Rising Edge (Daisy-Chain Mode)

2

ns

Valid Hold Time from SCK Rising Edge (Daisy-Chain Mode)

2

ns

SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE)

12

ns

1

Timing parameters measured with respect to a falling edge are defined as triggered at X% VIO. Timing parameters measured with respect to a rising edge are defined

as triggered at Y% VIO. For VIO ≤ 2.7 V, X = 80, and Y = 20. For VIO > 2.7 V, X = 70, and Y = 30. The minimum VIH and maximum VIL are used. See Digital Inputs

Specifications in Table 1.

2

The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 1.8 MSPS for the

AD4020, 1 MSPS for the AD4021, and 500 kSPS for the AD4022.

3

4

A throughput rate of 1.8 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 71 MHz. Refer to Table 4 for the maximum achievable

throughput for different modes of operation. See the Serial Clock Frequency Requirements section for guidelines on determining the minimum SCK rate required for a

given throughput.

5

A 50% duty cycle is assumed for SCK.

6