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ADRF6604ACPZ-R7 数据表(PDF) 4 Page - Analog Devices |
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ADRF6604ACPZ-R7 数据表(HTML) 4 Page - Analog Devices |
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4 / 32 page  ADRF6604 Data Sheet Rev. B | Page 4 of 32 SYNTHESIZER/PLL SPECIFICATIONS VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fREF power = 4 dBm, fPFD = 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized using CDAC = 0xC and IP3SET = 3.3 V, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to 1× LO Frequency Range Internally generated LO 2500 2900 MHz Figure of Merit1 PREF_IN = 0 dBm −221.4 dBc/Hz/Hz Reference Spurs fPFD = 38.4 MHz fPFD/4 −107 dBc fPFD −82 dBc >fPFD −80 dBc PHASE NOISE fLO = 2500 MHz to 2900 MHz, fPFD = 38.4 MHz 1 kHz to 10 kHz offset −87.7 dBc/Hz 100 kHz offset −96 dBc/Hz 500 kHz offset −117 dBc/Hz 1 MHz offset −126 dBc/Hz 5 MHz offset −142 dBc/Hz 10 MHz offset −148 dBc/Hz 20 MHz offset −150 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth 0.69 °rms PFD Frequency 20 40 MHz REFERENCE CHARACTERISTICS REF_IN, MUXOUT pins REF_IN Input Frequency 12 160 MHz REF_IN Input Capacitance 4 pF MUXOUT Output Level VOL (lock detect output selected) 0.25 V VOH (lock detect output selected) 2.7 V MUXOUT Duty Cycle 50 % CHARGE PUMP Pump Current Programmable to 250 µA, 500 µA, 750 µA, 1 mA 500 µA Output Compliance Range 1 2.8 V 1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10 log 10(fPFD) – 20 log 10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz, and fREF power = 10 dBm (500 V/µs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset. LOGIC INPUT AND POWER SPECIFICATIONS VS = 5 V, ambient temperature (TA) = 25°C, fREF = 153.6 MHz, fPFD = 38.4 MHz, high-side LO injection, fIF = 140 MHz, IIP3 optimized using CDAC = 0xC and IP3SET = 3.3 V, unless otherwise noted. Table 4. Parameter Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS CLK, DATA, LE Input High Voltage, VINH 1.4 3.3 V Input Low Voltage, VINL 0 0.7 V Input Current, IINH/IINL 0.1 µA Input Capacitance, CIN 5 pF POWER SUPPLIES VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I pins Voltage Range 4.75 5 5.25 V Supply Current PLL only 96 mA External LO mode (internal PLL disabled, IP3SET pin = 3.3 V, LO output buffer off) 164 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer on) 274 mA Internal LO mode (internal PLL enabled, IP3SET pin = 3.3 V, LO output buffer off) 260 mA Power-down mode 30 mA |
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