ADRF6604

Data Sheet

Rev. B | Page 18 of 32

REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4)

CP

CURRENT

REF

SOURCE

PFD

POL

CP

SRC

DB23

DB22

DB21 DB20 DB19

DB18

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

RMS2 RMS1 RMS0

RS1

RS0

CPM

CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0

PE1

PE0

PAB1 PAB0 C3(1)

C2(0)

C1(0)

CPC1 CPC0

0

0

0

1

1

0

1

1

CPS

0

1

CPP1 CPP0

0

0

0

1

1

0

1

1

CPB4 CPB3 CPB2 CPB1

CPB0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

0

0

1

0

1

0

1

0

0

0

0

1

1

1

1

1

CPBD

0

1

CPM

0

1

RS1

RS0

0

0

0

1

1

0

1

1

RMS2 RMS1 RMS0

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

PFD PHASE OFFSET MULTIPLIER

BOTH ON

PUMP DOWN

PUMP UP

TRISTATE (DEFAULT)

REF OUTPUT

MUX SELECT

INPUT REF

PATH

PFD PHASE OFFSET

MULTIPLIER

CP

CURRENT

CP

CONTROL

PFD EDGE

CONTROL BITS

PFD ANTI-

BACKLASH

DELAY

PE0

0

1

REFERENCE PATH EDGE

SENSITIVITY

FALLING EDGE

RISING EDGE (DEFAULT)

PAB1 PAB0

0

0

0

1

1

0

1

1

PFD ANTIBACKLASH

DELAY

0ns (DEFAULT)

0.5ns

0.75ns

0.9ns

CHARGE PUMP CONTROL

0.5 × REFIN (BUFFERED)

CHARGE PUMP CONTROL SOURCE

CONTROL BASED ON STATE OF DB7 AND DB8 (CP CONTROL)

CONTROL FROM PFD (DEFAULT)

REF OUTPUT MUX SELECT

LOCK DETECT (DEFAULT)

VPTAT

REF_IN (BUFFERED)

PFD PHASE OFFSET POLARITY

NEGATIVE

POSITIVE (DEFAULT)

CHARGE PUMP CURRENT

REFERENCE SOURCE

INTERNAL (DEFAULT)

EXTERNAL

0.25 × REFIN

CHARGE PUMP CURRENT

250µA

500µA (DEFAULT)

750µA

1000µA

INPUT REFERENCE

PATH SOURCE

2 × REFIN

REFIN (DEFAULT)

0.5 × REFIN

2 × REFIN (BUFFERED)

TRISTATE

RESERVED

RESERVED

PE1

0

1

DIVIDER PATH EDGE

SENSITIVITY

FALLING EDGE

RISING EDGE (DEFAULT)

Figure 42. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map