ADRF6604

Data Sheet

Rev. B | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

RF Specifications .......................................................................... 3

Synthesizer/PLL Specifications................................................... 4

Logic Input and Power Specifications ....................................... 4

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

RF Frequency Sweep .................................................................... 9

IF Frequency Sweep ................................................................... 10

Spurious Performance................................................................ 15

Register Structure ........................................................................... 16

Register 0—Integer Divide Control (Default: 0x0001C0)..... 16

Register 1—Modulus Divide Control (Default: 0x003001) ........16

Register 2—Fractional Divide Control (Default: 0x001802) ......17

Register 3—Σ-Δ Modulator Dither Control

(Default: 0x10000B) ................................................................... 17

Register 4—PLL Charge Pump, PFD, and Reference Path

Control (Default: 0x0AA7E4)................................................... 18

Register 5—PLL Enable and LO Path Control

(Default: 0x0000E5) ................................................................... 19

Register 6—VCO Control and VCO Enable

(Default: 0x1E2106) ................................................................... 19

Register 7—Mixer Bias Enable and External VCO Enable

(Default: 0x000007).................................................................... 19

Theory of Operation ...................................................................... 20

Programming the ADRF6604................................................... 20

Initialization Sequence .............................................................. 20

LO Selection Logic ..................................................................... 21

Applications Information .............................................................. 22

Basic Connections for Operation............................................. 22

AC Test Fixture ............................................................................... 23

Evaluation Board ............................................................................ 24

Evaluation Board Control Software......................................... 24

Schematic and Artwork............................................................. 26

Evaluation Board Configuration Options............................... 28

Outline Dimensions....................................................................... 29

Ordering Guide .......................................................................... 29

REVISION HISTORY

1/14—Rev. A to Rev. B

Change to Product Title................................................................... 1

Updated Outline Dimensions (Lead-to-Pad Dimension)......... 29

5/11—Rev. 0 to Rev. A

Changes to Features and General Description Sections.............. 1

Changes to Table 2............................................................................ 3

Changes to Synthesizer Specifications Parameter and to Phase

Noise Parameter, Table 3 ............................................................. 4

Changes to Power Supplies Parameter, Table 4 ............................ 4

Replaced Typical Performance Characteristics Section;

Renumbered Sequentially ........................................................... 9

Added Spurious Performance Section......................................... 15

Change to Figure 41 ....................................................................... 17

Changes to Figure 42...................................................................... 18

Changes to Theory of Operation Section.................................... 20

Changes to Figure 46...................................................................... 22

Added AC Test Fixture Section and Figure 47 ........................... 23

Changes to Evaluation Board Control Software Section and

Figure 48 ...................................................................................... 24

Changes to Figure 49...................................................................... 25

6/10—Revision 0: Initial Version