ADRF6604ACPZ-R7 datasheet(20/32 Pages) AD

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ADRF6604

Data Sheet

Rev. B | Page 20 of 32

THEORY OF OPERATION

The ADRF6604 integrates a high performance downconverting

mixer with a state-of-the-art fractional-N PLL. The PLL also

integrates a low noise VCO. The SPI port allows the user to control

the fractional-N PLL functions and the mixer optimization

functions, as well as allowing for an externally applied LO or VCO.

The mixer core within the ADRF6604 is the next generation of

an industry-leading family of mixers from Analog Devices, Inc.

The RF input is converted to a current and then mixed down to IF

using high performance NPN transistors. The mixer output currents

are transformed to a differential output. The high performance active

mixer core results in an exceptional IIP3 and IP1dB with a very

low output noise floor for excellent dynamic range. Over the

specified frequency range, the ADRF6604 typically provides IF

input P1dB of 14.5 dBm and IIP3 of 27.5 dBm.

Improved performance at specific frequencies can be achieved

with the use of the internal capacitor DAC (CDAC), which is

programmable via the SPI port, and by using a resistor to a 5 V

supply from the IP3SET pin (Pin 29). Adjustment of the capacitor

DAC allows increments in phase shift at internal nodes in the

ADRF6604, thus allowing cancellation of third-order distortion

with no change in supply current. Connecting a resistor to a 5 V

supply from the IP3SET pin increases the internal mixer core current,

thereby improving overall IIP2 and IIP3, as well as IP1dB. Using

the IP3SET pin for this purpose increases the overall supply current.

The fractional divide function of the PLL allows the frequency

multiplication value from REF_IN to LO output to be a fractional

value rather than to be restricted to an integer value as in tradi-

tional PLLs. In operation, this multiplication value is

INT + (FRAC/MOD)

where:

INT is the integer value.

FRAC is the fractional value.

MOD is the modulus value.

The INT, FRAC, and MOD values are all programmable via the

SPI port. In other fractional-N PLL designs, fractional multi-

plication is achieved by periodically changing the fractional value

in a deterministic way. The disadvantage of this approach is that

there are often spurious components close to the fundamental

signal. In the ADRF6604, a Σ-Δ modulator is used to distribute

the fractional value randomly, thus significantly reducing the

spurious content due to the fractional function.

PROGRAMMING THE ADRF6604

The ADRF6604 is programmed via a 3-pin SPI port. The timing

requirements for the SPI port are shown in Figure 2. Eight pro-

grammable registers, each with 24 bits, control the operation of

the device. The register functions are listed in Table 8.

Table 8. ADRF6604 Register Functions

Function

Integer divide control for the PLL

Modulus divide control for the PLL

Fractional divide control for the PLL

Σ-Δ modulator dither control

PLL charge pump, PFD, reference path control

PLL enable and LO path control

VCO control and VCO enable

Mixer bias enable and external VCO enable

Note that internal calibration for the PLL must be run when the

ADRF6604 is initialized at a given frequency. This calibration is

run automatically whenever Register 0, Register 1, or Register 2 is

programmed. Because the other registers affect PLL performance,

last and in the following order: Register 0, Register 1, Register 2.

To program the frequency of the ADRF6604, the user typically

programs only Register 0, Register 1, and Register 2. However,

if registers other than these are programmed first, a short delay

should be inserted before programming Register 0. This delay

ensures that the VCO band calibration has sufficient time to

complete before the final band calibration for Register 0 is initiated.

Software is available on the ADRF6604 product page under the

Evaluation Boards & Kits section that allows easy programming

from a PC running Windows® XP or Vista.

INITIALIZATION SEQUENCE

To ensure proper power-up of the ADRF6604, it is important to

reset the PLL circuitry after the VCC supply rail settles to 5 V ±

0.25 V. Resetting the PLL ensures that the internal bias cells are

properly configured, even under poor supply start-up conditions.

To ensure that the PLL is reset after power-up, use the following

procedure:

1. Disable the PLL by setting the PLEN bit to 0 (Register 5,

Bit DB6).

2. After a delay of >100 ms, set the PLEN bit to 1 (Register 5,

Bit DB6).

After this procedure is completed, the other registers should

be programmed in the following order: Register 7, Register 6,

of >100 ms, Register 0 should be programmed.

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