Data Sheet

ADRF6604

Rev. B | Page 7 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A

LOW IMPEDANCE GROUND PLANE.

1

VCC1

2

DECL3P3

3

CP

4

GND

5

6

REF_IN

7

GND

8

MUXOUT

9

DECL2P5

10

VCC2

23 GND

24 GND

25 GND

27 VCC_V2I

28 GND

29 IP3SET

30 GND

22 VCC_MIX

21 GND

TOP VIEW

(Not to Scale)

ADRF6604

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

VCC1

Power Supply for the 3.3 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.

2

DECL3P3

Decoupling Node for 3.3 V LDO. Connect a 0.1 µF capacitor between this pin and ground.

3

CP

Charge Pump Output Pin. Connect to VTUNE through the loop filter.

4, 7, 11, 15, 20,

21, 23, 24, 25,

28, 30, 31, 35

GND

Ground. Connect these pins to a low impedance ground plane.

5

Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA, 750 µA, or 1 mA using

Bit DB11 and Bit DB10 in Register 4 and by setting Bit DB18 in Register 4 to 0 (internal reference current). In

can be externally adjusted according to the following equation:

Ω

37.8

4

.

217

−













×

=

NOMINAL

CP

SET

I

I

R

6

REF_IN

Reference Input. Nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin is internally dc-

biased and should be ac-coupled.

8

MUXOUT

Multiplexer Output. This output can be programmed to provide the reference output signal or the lock detect

signal. The output is selected by programming the appropriate register.

9

DECL2P5

Decoupling Node for 2.5 V LDO. Connect a 0.1 µF capacitor between this pin and ground.

10

VCC2

Power Supply for the 2.5 V LDO. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin

should be decoupled with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.

12

DATA

Serial Data Input. The serial data input is loaded MSB first; the three LSBs are the control bits.

13

CLK

Serial Clock Input. The serial clock input is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. The maximum clock frequency is 20 MHz.

14

LE

Load Enable. When the LE input pin goes high, the data stored in the shift register is loaded into one of the

eight registers. The relevant latch is selected by the three control bits of the 24-bit word.

16

PLL_EN

PLL Enable. Switch between internal PLL and external LO input. When this pin is logic high, the mixer LO is

automatically switched to the internal PLL and the internal PLL is powered up. When this pin is logic low, the

internal PLL is powered down and the external LO input is routed to the mixer LO inputs. The SPI can also be

used to switch modes.

17, 34

VCC_LO

Power Supply. Power supply voltage range is 4.75 V to 5.25 V. Each power supply pin should be decoupled

with a 100 pF capacitor and a 0.1 µF capacitor located close to the pin.

18, 19

IFP, IFN

Mixer IF Outputs. These outputs should be pulled to VCC_MIX with RF chokes.