ADRF6720ACPZ-R7 datasheet(40/44 Pages) AD

部件名	ADRF6720ACPZ-R7

功能描述	Wideband Quadrature Modulator with Integrated Fractional-N PLL and VCOs

PDF	44 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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40 / 44 page

ADRF6720

Data Sheet

Table 28. Bit Descriptions for PFD_CP_CTL

Bits

Bit Name

Settings

Description

Reset

Access

[6:5]

ABLDLY

Set Antibacklash Delay.

0x0

0 ns.

0.5 ns.

0.75 ns.

0.9 ns.

[4:2]

CP_CTRL

Set Charge Pump Control.

0x4

000

Both On.

001

Pump Down.

010

Pump Up.

011

Tristate.

100

PFD.

[1:0]

PFD_CLK_EDGE

Set PFD Clock Edge Trigger.

0x0

Divide and Reference Down Edge.

Divide Down Edge, Reference Up Edge.

Divide Up Edge, Reference Down Edge.

Divide and Reference Up Edge.

Address: 0x42, Reset: 0x000E, Name: DITH_CTL1

Table 29. Bit Descriptions for DITH_CTL1

Bits

Bit Name

Settings

Description

Reset

Access

DITH_EN

Set Dither Enable.

0x1

Disable.

Enable.

[2:1]

DITH_MAG

Set Dither Magnitude.

0x3

DITH_VAL

Set Dither Value.

0x0

Address: 0x43, Reset: 0x0000, Name: DITH_CTL2

Table 30. Bit Descriptions for DITH_CTL2

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

DITH_VAL

Set Dither Value.

0x0

Rev. 0 | Page 40 of 44

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