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ADRF6720ACPZ-R7 数据表(PDF) 6 Page - Analog Devices |
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ADRF6720ACPZ-R7 数据表(HTML) 6 Page - Analog Devices |
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6 / 44 page  ADRF6720 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit PHASE NOISE, FREQUENCY = 2300 MHz, fPFD = 38.4 MHz Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter design) 10 kHz offset −94.1 dBc/Hz 100 kHz offset −114.6 dBc/Hz 1 MHz offset −138.7 dBc/Hz 5 MHz offset −150.1 dBc/Hz 10 MHz offset −151.4 dBc/Hz 20 MHz offset −152.6 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth, with spurs 0.270 ° rms Reference Spurs fPFD −100.8 dBc fPFD × 2 −95.6 dBc fPFD × 3 −89.4 dBc fPFD × 4 −93.1 dBc PHASE NOISE, FREQUENCY = 2600 MHz, fPFD = 38.4 MHz Closed-loop operation (20 kHz loop filter, see Figure 44 for loop filter design) 10 kHz offset −91.5 dBc/Hz 100 kHz offset −111.3 dBc/Hz 1 MHz offset −136.8 dBc/Hz 5 MHz offset −148.3 dBc/Hz 10 MHz offset −150 dBc/Hz 20 MHz offset −150.7 dBc/Hz Integrated Phase Noise 1 kHz to 40 MHz integration bandwidth, with spurs 0.378 °rms Reference Spurs fPFD −97.4 dBc fPFD × 2 −89.3 dBc fPFD × 3 −95.2 dBc fPFD × 4 −91.4 dBc LO INPUT/OUTPUT LO Output Frequency Range LO output 700 2855 MHz LO Output Level 2 × LO or 1 × LO mode, into a 50 Ω load, LO buffer enabled at 2140 MHz LO_DRV_LVL = 0 −5.1 dBm LO_DRV_LVL = 1 −0.5 dBm LO_DRV_LVL = 2 3 dBm LO Input Level Externally applied LO, PLL disabled −6 0 +6 dBm LO Input Impedance Externally applied LO, PLL disabled 50 Ω BASEBAND INPUTS I± and Q± pins I and Q Input DC Bias Level 0.5 V Bandwidth 1 dB >1000 MHz Differential Input Impedance Frequency = 10 MHz2 465 Ω Differential Input Capacitance Frequency = 10 MHz2 1.84 pF OUT ENABLE ENBL pin Turn-On Settling Time ENBL high to low (90% of envelope), when Register 0x01[10] = 1, Register 0x10[10] = 1 190 ns Turn-Off Settling Time ENBL low to high (10% of envelope), when Register 0x01[10] = 1, Register 0x10[10] = 1 20 ns Rev. 0 | Page 6 of 44 |
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