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ADRF6720ACPZ-R7 数据表(PDF) 7 Page - Analog Devices

部件名 ADRF6720ACPZ-R7
功能描述  Wideband Quadrature Modulator with Integrated Fractional-N PLL and VCOs
PDF  44 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADRF6720ACPZ-R7 数据表(HTML) 7 Page - Analog Devices

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Data Sheet
ADRF6720
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL LOGIC
SCLK, SDIO, CS, and ENBL
Input Voltage High (VIH)
1.4
V
Input Voltage Low (VIL)
0.7
V
Input Current (IIH/IIL)
−1
1
µA
Input Capacitance
(CIN)
5
pF
Output Voltage High
(VOH)
IOH = −100 uA
2.3
V
Output Voltage Low
(VOL)
IOL = 100 uA
0.2
V
POWER SUPPLIES
Voltage Range
VPOSx
3.3
V
Supply Current
Tx mode at internal LO mode (PLL, internal VCO , and modulator
enabled, LO output driver disabled)
425
mA
Tx mode at external 1× LO mode (PLL, internal VCO disabled,
modulator enabled, LO output driver disabled)
228
mA
LO output driver; LO_DRV_LVL bits (Register 0x22[7:6]) = 10
50
mA
Power-down mode
14.5
mA
1
The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(fPFD) − 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF =
153.6 MHz, fREF power = 4 dBm with a 38.4 MHz fPFD. The FOM was computed at a 50 kHz offset.
2
Refer to Figure 47 for a plot of input impedance over frequency.
TIMING CHARACTERISTICS
Table 2.
Parameter
Description
Min
Typ
Max
Units
tSCLK
Serial clock period
38
ns
tDS
Setup time between data and rising edge of SCLK
8
ns
tDH
Hold time between data and rising edge of SCLK
8
ns
tS
Setup time between falling edge of CS and SCLK
10
ns
tH
Hold time between rising edge of CS and SCLK
10
ns
tHIGH
Minimum period that SCLK should be in a logic high state
10
ns
tLOW
Minimum period that SCLK should be in a logic low state
10
ns
tACCESS
Maximum time delay between falling edge of SCLK and output data valid for a read operation
231
ns
tz
Maximum time delay between CS deactivation and SDIO bus return to high impedance
5
ns
Figure 2. Serial Port Timing Diagram
tS
tDS
tDH
tHIGH
tLOW
tSCLK
tH
DON'T CARE
DON'T CARE
A5
A4
A3
A2
A1
A0
D15
D14
D13
D3
D2
D1
D0
DON'T CARE
DON'T CARE
SCLK
SDIO
R/W
tZ
tACCESS
A6
CS
Rev. 0 | Page 7 of 44



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