ZPSD301 datasheet(67/85 Pages) STMICROELECTRONICS

67 / 85 page

PSD3XX Family

Figure 40. Port A as AD0–AD7 Timing (Track Mode) Using R/W, E or R/W, DS (PSD3X2/3X3)

DATA VALID

ADDRESS

READ CYCLE

WRITE CYCLE

STABLE INPUT

Direct

PAD Input

(1,4)

Multiplexed

PAD Inputs

(5,7)

A0/AD0-

A7/AD7

or AS

RD/E/DS as E

WR/VPP or

R/W as R/W

RD/E/DS as DS

PA0-PA7

CSOi

(3,6)

ADR OUT

DATA IN

DATA

OUT

WRITTEN

DATA

ADR OUT

1. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or

R/W, transparent PC0–PC2, ALE in non-multiplexed modes.

2. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS): A0/AD0–A15/AD15,

CSI/A19 as ALE dependent A19, ALE dependent PC0–PC2.

3. CSOi = any of the chip-select output signals coming through Port B (CS0–CS7) or through Port C

(CS8–CS10).

4. CSADOUT1, which internally enables the address transfer to Port A, should be derived only from direct PAD

input signals, otherwise the address propagation delay is slowed down.

5. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively, can be

derived from any combination of direct PAD inputs and multiplexed PAD inputs.

6. The write operation signals are included in the CSOi expression.

7. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in the multiplexed

modes: A11/AD11–A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PC0–PC2.

8. CSOi product terms can include any of the PAD input signals shown in Figure 3, except for reset and CSI.

Notes for

Timing

Diagrams

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