ZPSD301 datasheet(34/85 Pages) STMICROELECTRONICS

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PSD3XX Family

16.

Power

Management

(cont.)

16.3 Turbo Bit (ZPSD only)

The turbo bit is controlled by the MCU at run-time and is accessed through bit zero of the

Power Management Register (PMR). The PMR is located in CSIOPORT space at offset 10h.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

***

Turbo bit

1= OFF

Power Management Register (PMR)

*Future Configuration bits are reserved and should be set to one when writing to this register.

The default value at reset of all bits in the PMR is logic 0, which means the Turbo feature is

enabled. The PAD logic (PAD A and PAD B) of the PSD will operate at full speed and full

power. When the Turbo Bit is set to logic 1, the Turbo feature is disabled. When disabled,

the PAD logic will draw only standby current (micro-amps) while no PAD inputs change.

Whenever there is a transition on any PAD input (including MCU address and control

signals), the PAD logic will power up and will generate new outputs, latch those outputs,

then go back to Standby Mode. Keep in mind that the signal propagation delay through the

PAD logic increases by 10 nsec for non-V devices, and 20 nsec for V devices while in

non-turbo mode. Use of the Turbo Bit does not affect the operation or power consumption

of memory.

Tremendous power savings are possible by setting the Turbo Bit and going into non-turbo

mode. This essentially reduces the DC power consumption of the PAD logic to zero. It also

reduces the AC power consumption of PAD logic when the composite frequency of all PAD

inputs change at a rate less than 40 MHz for non-V devices, and less than 20 MHz for V

devices. Use Figures 14 and 15 to calculate AC and DC current usage in the PAD with the

Turbo Bit on and off. You will need to know the number of product terms that are used in

your design and you will have to calculate the composite frequency of all signals entering

the PAD logic.

16.4 Number of Product Terms in the PAD Logic

The number of product terms used in your design relates directly to how much current the

PADs will draw. Therefore, minimizing this number will be in your best interest if power is a

concern for you. Basically, the amount of product terms your design will use is based on the

following (see Figure 4):

• Each of the EPROM block selects, ES0-ES7 uses one product term (for a total of 8).

• The CSIOPORT select uses one product term.

• If your part has SRAM (non-R versions), the SRAM select RS0 uses one product term.

• The Track Mode control signals (CSADIN, CSADOUT1, and CSADOUT2) each use

one product term if you use these signals.

• Port B, pins PB0-PB3 are allocated four product terms each if used as outputs.

• Port B, pins PB4-PB7 are allocated two product terms each if used as outputs.

• Port C, pins PC0-PC2 are allocated one product term each if used as outputs.

Given the above product term allocation, keep the following points in mind when calculating

the total number of product terms your design will require:

1) The EPROM block selects, CSIOPORT select, and SRAM select will use a product term

whether you use these blocks or not. This means you start out with 10 product terms,

and go up from there.

2) For Port B, if you use a pin as an output and your logic equation requires only one

product term, you still have to include all the available product terms for that pin for

power consumption, even though only one product term is specified. For example, if the

output equation for pin PB0 uses just one product term, you will have to count PB0 as

contributing four product terms to the overall count. With this in mind, you should use

Port C for the outputs that only require one product term and PB4-7 for outputs that

require two product terms. Use pins PB0-3 if you need outputs requiring more than two

product terms or you have run out of outputs.

3) The following PSD functions do not consume product terms: MCU I/O mode, Latched

Address Output, and PAD inputs (logic or address).

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