ZPSD301 datasheet(30/85 Pages) STMICROELECTRONICS

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PSD3XX Family

14.0

System

Applications

In Figure 11, the PSD3XX is configured to interface with Intel’s 80C31, which is a 16-bit

address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order

address byte. The 80C31 uses signals RD to read from data memory and PSEN to read

from code memory. It uses WR to write into the data memory. It also uses active high reset

and ALE signals. The rest of the configuration bits, as well as the unconnected signals,

are application specific, and thus, user dependent.

MICROCONTROLLER

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

PSEN

ALE

TXD

RXD

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PC0

PC1

PC2

A19/CSI

EA/VP

RESET

INT0

INT1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

AD0/A0

AD1/A1

AD2/A2

AD3/A3

AD4/A4

AD5/A5

AD6/A6

AD7/A7

AD8/A8

AD9/A9

AD10/A10

AD11/A11

AD12/A12

AD13/A13

AD14/A14

AD15/A15

WR/VPP

BHE/PSEN

ALE

RESET

GND

PSD3XX

80C31

VCC

0.1µF

Reset

NOTE: RESET to the PSD3XX must be the output of a RESET chip or buffer.

If RESET to the 80C31 is the output of an RC circuit, a separate buffered RC RESET to the

PSD3XX (shorter than the 80C31 RC RESET) must be provided to avoid a race condition.

Figure 11. PSD3XX Interface With Intel’s 80C31

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